Category: Datasheet/Specs
Product Number: ADRV9004
We have an application using the ADRV9004 to do fast frequency hopping and requires deterministic latency between both data paths within a single ADRV.
Unfortunately, I missed reading the Multichip Synchronization section within the ADRV System Development User Guide. It appears that a source synchronize clock with the reference clock is required to feed the ADRV's MCS.
If there isn't an MCS Clock, what variation/spread in RF channel delays might we expect?
If we are providing a 200MHz reference clock, would a 5 to 10KHz 50% duty cycle clock be sufficient for the MCS clock?
