ADRV9002 MCS using external LO

Hello

I an using two ADRV9002 evaluation boards on a ZCU102. An HMC7044 evaluation board is used to generate the device clock and MCS pulses to the ADRV9002 evaluation boards. The setup is described in full here:

ez.analog.com/.../linux-driver-support-for-multichip-synchronisation-across-two-adrv9002-evaluation-boards

Initially I did my testing with the internal LOs. Using the internal LOs, I am able to successfully complete multi-chip synchronisation (MCS). This is the output when using internal LOs:

root@adrv9002rrs:~# ./runmcs.sh
Running MCS on ADRV9002 1 in background...
Running MCS on ADRV9002 2 in background...
Generating MCS pulse 1...
Generating MCS pulse 2...
Generating MCS pulse 3...
Generating MCS pulse 4...
Generating MCS pulse 5...
Generating MCS pulse 6...
ADRV9002 1 MCS status...
rf1PllSyncStatus.jesdSyncComplete: 1
rf1PllSyncStatus.digitalClocksSyncComplete: 1
rf1PllSyncStatus.clockGenDividerSyncComplete: 1
rf1PllSyncStatus.sdmClockDividerSyncComplete: 1
rf1PllSyncStatus.referenceClockDividerSyncComplete: 1
rf2PllSyncStatus.jesdSyncComplete: 1
rf2PllSyncStatus.digitalClocksSyncComplete: 1
rf2PllSyncStatus.clockGenDividerSyncComplete: 1
rf2PllSyncStatus.sdmClockDividerSyncComplete: 1
rf2PllSyncStatus.referenceClockDividerSyncComplete: 1
clkPllSyncStatus.jesdSyncComplete: 1
clkPllSyncStatus.digitalClocksSyncComplete: 1
clkPllSyncStatus.clockGenDividerSyncComplete: 1
clkPllSyncStatus.sdmClockDividerSyncComplete: 1
clkPllSyncStatus.referenceClockDividerSyncComplete: 1
clkPllLpSyncStatus.jesdSyncComplete: 0
clkPllLpSyncStatus.digitalClocksSyncComplete: 0
clkPllLpSyncStatus.clockGenDividerSyncComplete: 0
clkPllLpSyncStatus.sdmClockDividerSyncComplete: 0
clkPllLpSyncStatus.referenceClockDividerSyncComplete: 0
firstDigitalSyncComplete: 1
secondDigitalSyncComplete: 1
rfPll1Phase_degrees: 0
rfPll2Phase_degrees: 0
ADRV9002 2 MCS status...
rf1PllSyncStatus.jesdSyncComplete: 1
rf1PllSyncStatus.digitalClocksSyncComplete: 1
rf1PllSyncStatus.clockGenDividerSyncComplete: 1
rf1PllSyncStatus.sdmClockDividerSyncComplete: 1
rf1PllSyncStatus.referenceClockDividerSyncComplete: 1
rf2PllSyncStatus.jesdSyncComplete: 1
rf2PllSyncStatus.digitalClocksSyncComplete: 1
rf2PllSyncStatus.clockGenDividerSyncComplete: 1
rf2PllSyncStatus.sdmClockDividerSyncComplete: 1
rf2PllSyncStatus.referenceClockDividerSyncComplete: 1
clkPllSyncStatus.jesdSyncComplete: 1
clkPllSyncStatus.digitalClocksSyncComplete: 1
clkPllSyncStatus.clockGenDividerSyncComplete: 1
clkPllSyncStatus.sdmClockDividerSyncComplete: 1
clkPllSyncStatus.referenceClockDividerSyncComplete: 1
clkPllLpSyncStatus.jesdSyncComplete: 0
clkPllLpSyncStatus.digitalClocksSyncComplete: 0
clkPllLpSyncStatus.clockGenDividerSyncComplete: 0
clkPllLpSyncStatus.sdmClockDividerSyncComplete: 0
clkPllLpSyncStatus.referenceClockDividerSyncComplete: 0
firstDigitalSyncComplete: 1
secondDigitalSyncComplete: 1
rfPll1Phase_degrees: 0
rfPll2Phase_degrees: 0
root@adrv9002rrs:~#

I then switched over to using a profile which uses an external LO. I got the two ADRV9002 devices booting up and working correctly with the external LO.

The problem is that now when I try to run multi-chip synchronisation with the external LO, the MCS procedure times out and does not complete successfully:

root@adrv9002rrs:~# ./runmcs.sh
Running MCS on ADRV9002 1 in background...
Running MCS on ADRV9002 2 in background...
Generating MCS pulse 1...
Generating MCS pulse 2...
Generating MCS pulse 3...
Generating MCS pulse 4...
Generating MCS pulse 5...
Generating MCS pulse 6...
ADRV9002 1 MCS status...
./runmcs.sh: line 5: echo: write error: Connection timed out
./runmcs.sh: line 3: echo: write error: Connection timed out
rf1PllSyncStatus.jesdSyncComplete: 1
rf1PllSyncStatus.digitalClocksSyncComplete: 1
rf1PllSyncStatus.clockGenDividerSyncComplete: 1
rf1PllSyncStatus.sdmClockDividerSyncComplete: 0
rf1PllSyncStatus.referenceClockDividerSyncComplete: 1
rf2PllSyncStatus.jesdSyncComplete: 1
rf2PllSyncStatus.digitalClocksSyncComplete: 1
rf2PllSyncStatus.clockGenDividerSyncComplete: 1
rf2PllSyncStatus.sdmClockDividerSyncComplete: 0
rf2PllSyncStatus.referenceClockDividerSyncComplete: 1
clkPllSyncStatus.jesdSyncComplete: 1
clkPllSyncStatus.digitalClocksSyncComplete: 1
clkPllSyncStatus.clockGenDividerSyncComplete: 1
clkPllSyncStatus.sdmClockDividerSyncComplete: 1
clkPllSyncStatus.referenceClockDividerSyncComplete: 1
clkPllLpSyncStatus.jesdSyncComplete: 0
clkPllLpSyncStatus.digitalClocksSyncComplete: 0
clkPllLpSyncStatus.clockGenDividerSyncComplete: 0
clkPllLpSyncStatus.sdmClockDividerSyncComplete: 0
clkPllLpSyncStatus.referenceClockDividerSyncComplete: 0
firstDigitalSyncComplete: 1
secondDigitalSyncComplete: 1
rfPll1Phase_degrees: 0
rfPll2Phase_degrees: 0
ADRV9002 2 MCS status...
rf1PllSyncStatus.jesdSyncComplete: 1
rf1PllSyncStatus.digitalClocksSyncComplete: 1
rf1PllSyncStatus.clockGenDividerSyncComplete: 1
rf1PllSyncStatus.sdmClockDividerSyncComplete: 0
rf1PllSyncStatus.referenceClockDividerSyncComplete: 1
rf2PllSyncStatus.jesdSyncComplete: 1
rf2PllSyncStatus.digitalClocksSyncComplete: 1
rf2PllSyncStatus.clockGenDividerSyncComplete: 1
rf2PllSyncStatus.sdmClockDividerSyncComplete: 0
rf2PllSyncStatus.referenceClockDividerSyncComplete: 1
clkPllSyncStatus.jesdSyncComplete: 1
clkPllSyncStatus.digitalClocksSyncComplete: 1
clkPllSyncStatus.clockGenDividerSyncComplete: 1
clkPllSyncStatus.sdmClockDividerSyncComplete: 1
clkPllSyncStatus.referenceClockDividerSyncComplete: 1
clkPllLpSyncStatus.jesdSyncComplete: 0
clkPllLpSyncStatus.digitalClocksSyncComplete: 0
clkPllLpSyncStatus.clockGenDividerSyncComplete: 0
clkPllLpSyncStatus.sdmClockDividerSyncComplete: 0
clkPllLpSyncStatus.referenceClockDividerSyncComplete: 0
firstDigitalSyncComplete: 1
secondDigitalSyncComplete: 1
rfPll1Phase_degrees: 0
rfPll2Phase_degrees: 0
root@adrv9002rrs:~#

Questions:

1) Should the ADC9002 MCS driver work correctly when using an external LO?

2) I found the following statement on another forum post:

ez.analog.com/.../external-lo-and-mcs

"Please note that there will always be phase ambiguity introduced by divider for external LO circuit so the LO phase is not synchronized, while the latency of digital part is synchornized between channels."

Does this mean that the divide by 2 on the external LO input is NOT synchronised by MCS?

Any advice would be greatly appreciated.

Thank you.

Gavin