[ADRV9002] Relationship of the TX DCLK and TX STRB

Hi,

We will get back to you.

Regards

Rahul 

Hi 

Could you please clarify the question again? 

In general sense, for the successful operation of SSI, the clock and the strobe signal has to be in the same phase. The main thing that needs to be considered here is that the alignment of clock and strobe signal, since this will decide the proper transmission and reception of the signal. The strobe signal is an indication for the starting bit, if the strobe and clock is delayed as shown in the below figure then the data received/transmission will be messed up.

Regards,

Rahul 

Thank you for your interest.

There was a problem with your question. I'm using it as a DDR setup, and SSI Strobe is setting to Long.

My question is, if there is a lot of delay in TX DCLK, so falling edge of TX_DCLK occurs at the start bit of Strobe signal, I wonder if it is a problem.

In the current experiment, if delay is artificially given, 6dB increases and debuggings are under way.