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[ADRV9002] Relationship of the TX DCLK and TX STRB

Category: Software
Product Number: ADRV9002
Software Version: 25.0

Hi, I'm posting a question while running the adrv9002 related system.

I think the rising edges of TX_DCLK_IN and TX_STROBE_IN should operate in the same phase as in the picture below, but I wonder if too much delay is applied to TX_DCLK_IN so it doesn't matter if the rising edge of TX_DCLK_IN comes from the falling edge of TX_DCLK_IN.

Thank you for your interest.

Thread Notes

  • Hi,

    We will get back to you.

    Regards

    Rahul 

  • Hi 

    Could you please clarify the question again? 

    In general sense, for the successful operation of SSI, the clock and the strobe signal has to be in the same phase. The main thing that needs to be considered here is that the alignment of clock and strobe signal, since this will decide the proper transmission and reception of the signal. The strobe signal is an indication for the starting bit, if the strobe and clock is delayed as shown in the below figure then the data received/transmission will be messed up.

    Regards,

    Rahul 

  • Thank you for your interest.

    There was a problem with your question. I'm using it as a DDR setup, and SSI Strobe is setting to Long.

    My question is, if there is a lot of delay in TX DCLK, so falling edge of TX_DCLK occurs at the start bit of Strobe signal, I wonder if it is a problem.

    In the current experiment, if delay is artificially given, 6dB increases and debuggings are under way.

  • Hi,

    We are currently auditing our engineerzone forums for questions that have not been fully answered. If any more information is needed, please reply to this post or create a new post.

    As indicated, if there is too much delay on an SSI line, the data could become clocked by the wrong clock edge. This would cause issues with bits being missed or misplaced. Generally, SSI traces should have identical length in order to avoid this issue. It is possible to add delays to the data ports to introduce addition delay in order to synchronize the data at the destination. Please refer to the user guide sections "SSI TIMING PARAMETERS", "CSSI/LSSI TESTABILITY AND DEBUG" for further details on this. There is also an FPGA SSI calibrated given in the SDK which can be observed in the autogenerated code. This can be used as an example for aligning SSI data through delays.

    Regards,

    Conrad