ADRV9002
Recommended for New Designs
The ADRV9002 is a highly integrated RF transceiver that has dual-channel transmitters, dual-channel receivers, integrated synthesizers, and digital signal...
Datasheet
ADRV9002 on Analog.com
HMC7044
Recommended for New Designs
The HMC7044 is a high performance, dual-loop, integer-N jitter attenuator capable of performing reference selection and generation of ultralow phase noise...
HMC7044 on Analog.com
Hello
We are planning on evaluating the multichip synchronisation of the ADRV9002 using two ADRV9002 evaluation boards on the ZCU102 with an HMC7044 evaluation board as the device clock and MCS pulse source. Below is a block diagram showing our proposed connections:
I have searched the forums and the only similar example I can find is that of the Jupiter SDR:
For the Jupiter SDR, a Synchrona was used to generate the device clocks and MCS request pulses. The device clock outputs from the Synchrona connect directly to the ADRV9002 as expected. However, the MCS request pulses are rather sent from the Synchrona to the FPGA, and then the FPGA generates the MCS to the ADRV9002.
Why is the MCS request pulses sent from the Synchrona to the FPGA first instead of directly to the ADRV9002?
We are planning on using the SCLKOUT outputs of the HMC7044 evaluation board to drive the MCS pulses to the DEVMCS_IN inputs of the ADRV9002 evaluation boards. Do you see any potential problem in driving the MCS inputs directly from the HMC7044, rather than via the FPGA (as is done in the Jupiter SDR example)?
Thank you.
Gavin
