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ADRV9002_ZCU102 Calibration Issue

Category: Software
Product Number: ADRV9002
Software Version: Vivado 2022.2

Hi Team,

                  I am using ZCU102_ADRV9002 Hardware and no_OS_2022_R2 , hdl_2022_R2. I configured 1TX1RX Mode CSSI with sampling rate of 1.92Msps and data rate of 61.44Mbps.
The no-OS  initialization prints are observed correctly. Both DAC and ADC are successfully initialized. The transmitter side (DAC) is working perfectly but at receiver side (ADC) , i added the adc_1_data_i0, adc_1_data_q0 , adc_1_data_i1, and adc_1_data_q1 of axi_adrv9001 to ILA ,, I observed Zero's most of the times and some kind of noise after some time and then again zero's in receiver output at ILA. Even though generating signal and providing it to RX side , it won't shows any affect. Are there any suggestions how to solve this issue? The RX1 is not working properly. One more thing is I am trying to program it, the following calibration is not passing


I have masked this calibration,

but I am unable receive any data through RX port(checking I Q samples in ILA)

If I mask this bit(0x1BE5F7 to 0x0BE57F) TX is working perfectly but RX side I am not observing anything. Using adi_adrv9001_Ssi_Rx_TestMode_Configure API , I sent ADI_ADRV9001_SSI_TESTMODE_DATA_RAMP_NIBBLE test data and able to receive at RX side (FPGA ILA end). Everything is fine except the ADI_ADRV9001_INIT_CAL_RX_GAIN_PATH_DELAY calibration.

Any suggestions would be helpful for further debugging.

Thanks in advance
 Goli Ganesh

  • Hi Ganesh,

    Regarding your first issue, assuming by data rate you mean interface data rate. Why do you have such a large interface rate with sample rate as little as 1.92MSPS? To be on the safe side, I would use TES to enter the required sampling rate (1.92MSPS) and use the default interface rate calculated by TES (happens to be also 1.92MSPS).

    However, if I try to do it your way (sampling rate = 1.92MSPS, interface rate=61.44MSPS) TES gives this warning message: "By default, Interface Rate is equal to Dataport Sampling Rate. If a different rate is desired, you must supply a custom PFIR under Rx Filters tab in order to achieve the intended Interface Rate."

    Are you running continuous receive (FDD) or TDD? User guide, page 331, "TDD Parameter Table" section explains how data could be lost or how you may end up with 0s on transmit side (similar should apply in reverse on receive side), if DMA/TDD is improperly configured. So make sure data isn't overflowing at any of the queues in your HDL design.



  • hi  ,

      Thank you for the response. My issue is initial calibrations are not happening at receiver side. What could be the reason for failing of ADI_ADRV9001_INIT_CAL_RX_GAIN_PATH_DELAY  calib.

    No other issues i have. Only thing calibration is not happening properly. 

    Thanks and regards
    Goli Ganesh

  • Hi  ,

    First thing that falls to mind is that there should be no input signal to Rx during initial calibration. There have been several reported issues related to failing ADI_ADRV9001_INIT_CAL_RX_GAIN_PATH_DELAY calibration such as:

    adi_adrv9001_cals_InitCals_Run fails when calibrating with ADI_ADRV9001_INIT_CAL_RX_GAIN_PATH_DELAY option - Q&A - Design Support ADRV9001 – ADRV9007 - EngineerZone (

    If you search for this define, ADI_ADRV9001_INIT_CAL_RX_GAIN_PATH_DELAY, you should find plenty of useful advice. Please let us know if any of that helps.



  • Hi  ,

           Thank you for the response.I already have went through those links. I obserevd that in our custom schematic VANA1_1P0 , VANA2_1P0 , VTX2LO_1P0, VTX1LO_1P0 were NCs and VRFLO1_1P0, VRFLO2_1P0 were connected to GND with respect to VRFVCO1_1P0, VRFVCO2_1P0. Is these connections were correct? Is there any necessity to provide 1.0V to VRFLO1_1P0 and VRFLO2_1P0 ?  And we are not using VDDA_1P0 in our design. Instead of VDDA_1P0 we are using VDDA_1P3. Is there any necessity to use of VDDA_1P0?

    Thanks and Regards
    Goli Ganesh