ADRV9002_ZCU102 Calibration Issue

Hi Ganesh,

Regarding your first issue, assuming by data rate you mean interface data rate. Why do you have such a large interface rate with sample rate as little as 1.92MSPS? To be on the safe side, I would use TES to enter the required sampling rate (1.92MSPS) and use the default interface rate calculated by TES (happens to be also 1.92MSPS).

However, if I try to do it your way (sampling rate = 1.92MSPS, interface rate=61.44MSPS) TES gives this warning message: "By default, Interface Rate is equal to Dataport Sampling Rate. If a different rate is desired, you must supply a custom PFIR under Rx Filters tab in order to achieve the intended Interface Rate."

Are you running continuous receive (FDD) or TDD? User guide, page 331, "TDD Parameter Table" section explains how data could be lost or how you may end up with 0s on transmit side (similar should apply in reverse on receive side), if DMA/TDD is improperly configured. So make sure data isn't overflowing at any of the queues in your HDL design.

Best,

Stefan

hi  ,


  Thank you for the response. My issue is initial calibrations are not happening at receiver side. What could be the reason for failing of ADI_ADRV9001_INIT_CAL_RX_GAIN_PATH_DELAY  calib.


No other issues i have. Only thing calibration is not happening properly. 


Thanks and regards
Goli Ganesh

Hi Ganesh_Goli ,

First thing that falls to mind is that there should be no input signal to Rx during initial calibration. There have been several reported issues related to failing ADI_ADRV9001_INIT_CAL_RX_GAIN_PATH_DELAY calibration such as:

adi_adrv9001_cals_InitCals_Run fails when calibrating with ADI_ADRV9001_INIT_CAL_RX_GAIN_PATH_DELAY option - Q&A - Design Support ADRV9001 – ADRV9007 - EngineerZone (analog.com)

If you search for this define, ADI_ADRV9001_INIT_CAL_RX_GAIN_PATH_DELAY, you should find plenty of useful advice. Please let us know if any of that helps.

Best,

Stefan

Hi  ,


       Thank you for the response.I already have went through those links. I obserevd that in our custom schematic VANA1_1P0 , VANA2_1P0 , VTX2LO_1P0, VTX1LO_1P0 were NCs and VRFLO1_1P0, VRFLO2_1P0 were connected to GND with respect to VRFVCO1_1P0, VRFVCO2_1P0. Is these connections were correct? Is there any necessity to provide 1.0V to VRFLO1_1P0 and VRFLO2_1P0 ?  And we are not using VDDA_1P0 in our design. Instead of VDDA_1P0 we are using VDDA_1P3. Is there any necessity to use of VDDA_1P0?


Thanks and Regards
Goli Ganesh

Hi,

We are currently auditing our engineerzone forums for questions that have not been fully answered. If any more information is needed, please reply to this post or create a new post.

The ADRV9002 evaluation board can be used as an example for power supply design. We recommend reviewing the 'POWER-SUPPLY RECOMMENDATIONS' section of the user guide for design and debug. The VDDA_1P0 power domain is optional and is suggested for use only to achieve minimum power consumption. This is not a required domain.

The in-system debugging API can also be useful to test if the device has powered up correctly. Review the 'SYSTEM DEBUGGING' section for further information on this.

Regards,

Conrad