Evaluation of multiple transceivers

Hi rahulpillai,

In some cases, for example, if your 4 antennas configuration is 2 receiver and 2 transmit (TDD or FDD), or 4 receiver (TDD with Rx port switching), you may be able to do this one on board.

There is currently no eval board with two ADRV9002 transceivers. If you'd like to evaluate more than 2 transceiver channels, you'll need more than one board.

Kind Regards,
Michał

Hey, thanks for replying.

My application is simplex there is no transmission, all the 4 antenna elements acts as receivers.

What I am expecting is to receive signals from the 4 antenna elements and send it to FPGA for processing.

If i need two evaluation boards, and all 4 receivers in the two boards are set to 2-lane LSSI with lane data rate of 983MHz per receiver channel, so, the bandwidth of one board will be around 2 * 983Mhz = 1.9Gbps. The ZC706 evaluation board, in the website it is mentioned the FMC LPC port is capable of 1GT, is it 1 giga transfer as in 1Gbps or something else?. If the LPC FMC is only capable of 1Gbps and there is only 1 FMC HPC with 8GT how can i connect two boards?

PS: I am a beginner in working with advanced ICs, a detailed response with resource will be helpful

Thank you.

Hi rahulpillai,

Allow me to clarify: when Rx with port switching is in use, there is still only one data path for each Rx channel. The only difference is that you can change which antenna each channel is connected to.

However, it sounds like you'll need 4 data streams. We do not currently support this. Our FPGA image only supports using the ADRV9002 eval board on the first FMC connector, so even if you got two eval boards, it wouldn't work. You might have some luck asking the Linux Software Drivers forum though, they use a different FPGA image and different development path.

Kind Regards,
Michał

is it the same for ZCU102 as well?

any particular reason why the image supports only the first FMC connector? 

Hi rahulpillai,

Yes, it's the same for the ZCU102. Support for two FMC connectors was surplus to the requirements at the time that the FPGA image was being designed. We have since begun work on a dual ADRV9002 EVB, but there is currently no timeline for its release.

Kind Regards,
Michał