About the ADCs present in the ADRV9002

Hi Rahul 

ADRV9002 module consists of pair of highly linear performance ADCs and a pair of low-power ADCs as , illustrated in the Rx signal chain block diagram (Fig 1) below are used for capturing IQ signals.

                                                                                                Fig 1: Rx signal chain block diagram

The ADRV9001 supports three standard ADC clocks: ADC-H clock at 2211.84 MHz, ADC-M clock at 1474.56 MHz, and ADC-L clock at 1105.92 MHz, applicable to both high-performance (HP) and low-power (LP) ADCs (referenced in the user development guide page 141 of 351) also highlighted in the decimation stages block diagram (Fig 2). These sample rate are unrelated to the samples rate that the user provide at the data port interface which is maximum of 61.44MHz (highlighted in the decimation stages block diagram in blue color). One to be note that if arbitrary sample rate is chosen for data port sample rate then ADC/DAC sample rate will change slightly in accordance with the data port sample rate.

                                                                                         Fig 2: Decimation Stages Block Diagram

ADRV9002 incorporates various built-in auxiliary functions to enhance monitoring and control capabilities. These functions comprise auxiliary ADC (4x10 bits AuxADC), auxiliary DAC (4x12 bits AuxDAC). These components are integrated to streamline control tasks, such as static voltage measurements and temperature sensing. The clock rate for the AuxADC is 30.72 MSPS (as referenced in the user development guide page 243 of 351). It's important to note that these AuxADCs are not utilized for RF IQ signals. One of the use case of using AuxADC and Aux DAC is to have a power amplifier RAMP control (as referenced in the user development guide page 233 of 351).

More information on data converter resolution

• In case of AuxADC the ADCs are 10 bits meaning the number of steps will be 1024 (2¹⁰), since the reference voltage is 0.95V, so each bit will correspond to (1.8/(2¹⁰)) = approx. 927.7 µV.

Overall the performance of ADRV9002 is highly dependent on the use cases and specification of the ADCs, my colleague has authored an article detailing how to compute valuable performance metrics using the specifications. You can access the article here:

https://www.analog.com/en/resources/technical-articles/high-dynamic-range-rf-transceiver-solves-the-blocking-challenge.html

Regards,

Mushini

Hello Mushini,

Thank you for replying. 

Could you point out the details of HP and LPADC in the ADRV9002 datasheet(not the user guide)?

I couldn't find the page where it talks about the receiver ADC clocks and its resolution. At first I got confused with AuxADC as the receiver ADC, then later down the line when I read about the data interface in the datasheet, there they have mentioned 16-bits I/Q signals, I thought the resolution is 10-bits and the other 6-bits maybe zero padding. Reading the user guide solved the confusion for me.

But I would really appreciate it if you could point where I can read the details of the receiver ADC(HP&LPADC) in the datasheet.

Also if at all possible, could you provide the details on the working of 5-bit sigma-delta adc, like an article?

Sincerely,

rahulpillai

Hi Rahul,

Thank you for reaching out.

Our data sheets are designed to provide relevant specifications tailored to your needs. While we strive to include as much information as possible, it's important to note that datasheet provides only relevant information, as if it may not be an appropriate place for all this information. For more comprehensive insights and guidance, we recommend referring to our user development guides. These guides offer further information and assistance to ensure your needs are met effectively. Should you have any specific inquiries or require additional support, please don't hesitate to let us know. We're here to help.  Below, you'll find links to articles and an interactive tutorial that delve into the workings of delta sigma ADCs for better understanding.    

Articles for Delta Sigma ADCs

https://www.analog.com/media/en/technical-documentation/application-notes/292524291525717245054923680458171an283.pdf

https://www.analog.com/media/en/technical-documentation/application-notes/28715432842357460935458165408691an388.pdf

www.analog.com/.../behind-the-sigma-delta-adc-topology.html

Delta Sigma ADCs Interactive tutorial

www.analog.com/.../sigma-delta-adc-tutorial.html

Regards,

Mushini