State change to Prime fails

Hi soccerdude,

I can think of two reasons why the state change may fail:

1. Not all the channels that are being primed have completed all of the Init Cals

2. The part may not yet have registered that it is now in the calibrated state. Try adding a short delay before going to primed.

If that doesn't resolve the issue, then try running the in-system debugging APIs adi_adrv9001_Utilities_SystemDebugPreCalibrate and adi_adrv9001_Utilities_SystemDebugPostCalibrate to see if any other issues come up.

Kind Regards,
Michał

Thanks. I ran the debug utility.

On the cards with an issue it Prints  Check RF PLLs and then quits without finishing printing anything else.

On the cards without issue it passes with an RF PLL Ok.

we are not using an external LO by the way. Just an external 125mhz clock.

Would the RF PLL not being locked be an issue with the out input clock?

Hi soccerdude,

The two things that are known to have an effect on the PLL's ability to lock is the stability of the power supply during calibration (i.e. ensure that the supply voltage does not go out of spec during high current draw), and the DEV_CLK jitter performance.

Kind Regards,
Michał