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ADRV900x Xilinx interface IP - cutout TDD functionality / IP documentation

Category: Hardware
Product Number: ADRV900x

We have been using the ADI ADRV900x interface IP block with a Xilinx FPGA without problem.  However, our application does not use TDD mode and I see that a large proportion of this IP block in terms of synthesised logic is devoted to TDD functionality, this logic being redundant for us.  Is there any means of configuring the core without this TDD functionality ?  Alternatively, is there any detailed documentation for this IP, including details of the AXI registers so that I may rewrite it to just include the required functionality.