I am working with ADRV9002 Evaluation Board. For that, I have customized the FPGA reference design, removing all the DMA IP cores and including custom TX/RX AXI-Stream IP cores and a custom TDD HDL design that will include frequency hopping. When I say custom TDD design I mean that my custom design is generating HOP, TX_SETUP and RX_SETUP signals with specific constraints outside AXI ADRV9001 IP Core, so I have disconnected these outputs from the AXI ADRV9001 IP. These signals are generated inside my HDL IP Core.
For the software comanding the ADRV9001 initialization, I am generating the C99 sample code from the TES.
My question is: Do I need to configure the Auto TDD tab in the TES even if I am not using the HOP, TX_SETUP and RX_SETUP signals provided by the AXI ADRV9001 IP core?
I ask this because I am facing some problems related to the RX data, the same problem that is exposed in this post:
The answer for that post was that the Auto TDD state machine should be enabled, but I am not sure if that will solve my problem (at the moment is not solving it) as I am generating the FH signals externally to the AXI ADRV9001 IP core.
Thank you in advance!