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9002 dac clk from fpga 9001 side

Category: Hardware
Product Number: adrv9002

i have a 9002 setup for cmos 4 lane ddr.

so it should be doing 20 Msps. 

my question is on the 9001 side IP. 

How/where does the dac_clk get set to match the 9002?

there is an option in 9001 IP to use RX (adc clock) for tx (dac).

will that force the same clock to be used on both SSI directions and have it be controlled by 9002 config(via Spi)

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  • We can help you with the configuration of ADRV9002 via API command but the HDL is supported in the fpga forum.

    My suggestion woudl be,

    1. Verify TX and RX logics inside FPGA using loopback instead of going through ADRV9002

    2. Conifgure ADRV9002 in SSI loopback mode and see whether you are able to receive what you transmit.

    Does this make sense to you?

    -YH

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