9002 dac clk from fpga 9001 side

Are you using the hdl code from https://wiki.analog.com/resources/fpga/docs/hdl ? Those issue are handled in the different forum and I can move the case for you.

-YH

yes i am.

yes i am.

There is another case of you on TES forum:  9002 register settings for DAC Channel RATE  - is this the same case? If duplicated, I want to consolidate it, and sorry for the delay on that case.

Could you clarify followings?

- It seems that you use TES to generate the profile. Do you also generate the code from TES or do you use Linux or No-OS software package from github?

- When you mentioned " i do not think i have a good configuration for DACs" - could you clarify what exactly is not a good configuration?

- Could you clarify " controlled by 9002 config(via Spi)" - what software are you using?

I generate the code form TES. i make the profile then have it generate the C99 code.

My PL is using the HDL adrv9001 on a zedboard.

i configure the 9002 via API commands. Then i configure the PL adrv9001 from my own driver using data/files generated from C99 output of TES.

By Good Configuration meaning it is not acting like TES is telling me it should.

TES is set to 20 Msps for Tx and Rx. Interface and Data port are the same 20 Msps in 4 Lane CMOS DDR mode. 

In Vivado i can see with ILA that the dac_valid_i0 is not staying high. it goes high every other clock cycle.

However, the adc_1_valid_i0 signal is high all the time. That seems correct. I would think they should act the same since they are supposed to be configured the same way.

We can help you with the configuration of ADRV9002 via API command but the HDL is supported in the fpga forum.

My suggestion woudl be,

1. Verify TX and RX logics inside FPGA using loopback instead of going through ADRV9002

2. Conifgure ADRV9002 in SSI loopback mode and see whether you are able to receive what you transmit.

Does this make sense to you?

-YH