Hi chkishore,

Please check to make sure that the ADRV9002 has a clock source. Either verify that the clock source selector switch is set to "ON BOARD", or if you are providing an external clock source, it is connected to the DEVCLK_IN port, and is at the frequency specified in the profile that you're programming.

Kind Regards,
Michał

HI Michal

Thank you for your response as I have already mentioned that I checked the Device clock.

I did checked device clock at a particular resistor(R420 by reference schematic) we given the selection with switch "on board" clock is fine at that resistor, also we have given external clock source though devclk_in(j501) by selecting switch "external" it is also fine. But we did observe that devclk_out(device clock output) is not working at R741.

/resized-image/__size/2426x1994/__key/communityserver-discussions-components-files/939/dev_5F00_clk_5F00_out.png

/resized-image/__size/2426x1994/__key/communityserver-discussions-components-files/939/dev_5F00_clk_5F00_in.png

Regards,

chkishore.

Hi chkishore,

My apologies, I missed that. When you mentioned that you checked the power input, can you clarify exactly what it was that you checked? Thanks.

I just noticed that when your GUI connects, the silicon revision returns as 00, which suggests that while the FPGA can connect to the EEPROM, it cannot communicate with the ADRV9002 itself.

The point you mentioned about R741 is not an issue, as that resistor is used to connect to a test point. The clock resistors in your second image are DNI because the clock is AC coupled.

Can you verify that you've tried each step in the TES connection debugging guide? TES Connection Issues. Your problem is not one that I've encountered before, but it's possible that one of the steps mentioned may resolve it.

Kind Regards,
Michał

Hello Michal,

Thanks for your response it is helpful to us,

I am indeed getting silicon version as 00, I tried your suggestion and checked the checksum of navassa_zcu102.img which is fine so i think sd_card is not corrupted. I checked the forum for the silicon version 00.https://ez.analog.com/rf/wide-band-rf-transceivers/design-support-adrv9001-adrv9007/f/q-a/550054/why-adrv9002-silicon-revision-information-is-00

Can you suggest any further suggestions for this issue.

Thanks & Regards,

chkishore.

Hi chkishore,

When you mentioned that you checked the power input, can you clarify exactly what it was that you checked? Thanks.

The last thing I can suggest is that you try to bypass the TES and run C code directly on the FPGA. You can generate C sample code in the TES using demo mode (which does not require a hardware connection) using the following guide: Produce and Compile Sample C99 Code.

Failing that, I'm afraid my only other suggestion is to try a different ADRV9002 EVB.

Kind Regards,
Michał

Hi Michal

Thank you for your reply, I checked power inputs at 1v,1.3v,1.8v. to ADRV9002 and are within power supply range.

Thanks & Regards,

chkishore.

Hi chkishore,

Did you check these at the output of the power supplies, or at the inputs of the ADRV9002?

Kind Regards,
Michał

Hi MIchal

I am checking power at power supplies at power supply output and Thank you for your continued support, we are contemplating on getting a new board.

Thanks & Regards,

Ch Kishore

Hi Ch Kishore,

It may be worth checking these closer to the input of the ADRV9002 instead. Every power input pin on the ADRV9002 has a ferrite bead and a 1 uF decoupling capacitor, which you can probe. I suggest starting with the digital supplies first, as they are the most likely cause of this issue.

Kind Regards,
Michał