ADRV9002 HDL Design - OSERDESE3 TPWS Timing Violation

Hi savalos,

I'll look into this for you.

Kind Regards,
Michał

Dear M_Bugajski ,

Are there any news related to this topic?

Best regards,

Sergio.

Hi Sergio,

My Apologies. You mentioned that it works when you use the reference design in version 2019.2, but not when you generate your own design in version 2022.2. Is there a reason why you are working with two versions of Vivado? 

Kind Regards,
Michał

Dear M_Bugajski ,

We worked in Vivado 2019.2 just to generate the reference design as it is provided by ADI with no modifications, to check how it is generated. In our project, we need to work (project constraint) with Vivado 2022.2.

 Best regards,

Sergio.

Dear M_Bugajski ,

We worked in Vivado 2019.2 just to generate the reference design as it is provided by ADI with no modifications, to check how it is generated. In our project, we need to work (project constraint) with Vivado 2022.2.

 Best regards,

Sergio.

Hi Sergio,

Have you tried to generate the reference design with no modifications in Vivado 2022.2?
That should tell us whether or not the issue is with compatibility between the reference design and version 2022.2, or if the issue is caused by the modifications that you've made.

Kind Regards,
Michał

Dear M_Bugajski ,

As you suggested, I tried to generate the reference design in Vivado 2022.2. For that, I needed to perform the following changes in the specified files:

1. Change Vivado version at adrv9001-sdk\pkg\prototype\platform\bin\vivado_include.tcl:
   1. Vivado 2019.2.1 --> Vivado 2022.2
2. Change IP version at adrv9001-sdk\pkg\prototype\platform\library\axi_rxdma\hdl\axi_rxdma.v:
   1. axis_data_fifo_v2_0_2_top --> axis_data_fifo_v2_0_9_top
3. Change IPs version at adrv9001-sdk\pkg\prototype\platform\library\axi_rxdma\hdl\axi_txdma.v:
   1. axis_dwidth_converter_v1_1_19_axis_dwidth_converter --> axis_dwidth_converter_v1_1_26_axis_dwidth_converter
   2. axis_data_fifo_v2_0_2_top --> axis_data_fifo_v2_0_9_top

The resulting project in Vivado 2022.2 also has the TPWS violation:

It seems a problem with the version migration.

Best regards,

Sergio.

Hi Sergio,

I checked with our FPGA team, their line is that there should be no modifications required to run 2022.2.

However, I found what appears to be a mismatch between their code and the code that's distributed in the SDK, so I'm following up on that.

Kind Regards,
Michał

Dear M_Bugajski ,

Thank you for your reply. I will wait for your answer.

Best regards,

Sergio.

Hi Sergio,

I've submitted a ticket to update the HDL code that's packaged into the SDK - this will be resolved in a future release, but I don't have any insight into when this will happen.

Kind Regards,
Michał