Hi EZ,
I am working with ADRV9002 HDL reference design provided for adrv9001-sdk for ZCU102, available at:
adrv9001-sdk\pkg\prototype\platform\projects\adrv9001_zcu102
I have succesfully generated the reference design using Vivado 2019.2. Now, I am integrating in the design custom VHDL IPs to interface with the tx0/rx0 data ports (not using tx1/rx1). For that, I have deleted all the AXI DMA IP cores available in the reference design. I am using Vivado 2022.2. When I launch the bitstream generation for my custom design I am getting TPWS violation on the CLK pin of some OSERDESE3 primitives inside ADI's IP axi_adrv9001 (see images below):
The problem is that the timing violation is happening inside ADI's IP core. All the clock buffers (BUFGCTRL, both BUFGCE_DIV) and primitives (OSERDESE3) involved in the violation are placed by constraint to the same exact location they were in the reference design (see image below).
What I am observing is that the slack in the reference design of the same primitive is not to big (0.007 ns, see image below), so I think any sligth changes to the reference design can cause the new design to fail timing, as it is happening to me.
Any idea to solve this problem?
Thank you in advance!