I have a revc ADRV9002 ADI eval board and a zedboard.
We are writing our own drivers to interface with the 9002 using the API.
The SPI portion seems to be working fine.
My issue is the FPGA side of the 9001 IP Core.
I am trying to configure the Core to use 4 Lane CMOS DDR.
When i read registers from the core they seem correct. Like reg 0x1C and 0x0C , DDS disable, FPGA chip type, etc..
When i try to write to the Core it seems like the settings do not take effect. i.e. i can set to 4 lanes but when i read back its still 1.
I am writing to register 0x44 to set to DDR and 4 Lanes. But i always read 0x83 back instead of what i write.
Near the bottom of the wiki there is a mention that the Core should be in reset when changing these values.
I have read the reset register (or i think i am) at 0x40 offset and its always 0.
What am i missing to be able to use the register to configure the core?
