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ADRV9002 RX Data does not come out intermittently

Category: Hardware
Product Number: ADRV9002
hello


We are working on a 5GNR SideLink project using ADRV9002.
- Configure: TDD / Radio Control: Pin mode / freq: 5.9GHz RX data is not output intermittently as shown below. If there is no TX in the TDD section, RX data is output normally. If you set TX and RX as shown in the picture, RX Data will not be output. - Is there a minimum duration Time for RX and TX?
-
Can RX Enable and TX Enable overlap?
      

thank you
 
  • Hi benjamin405, 

    I'll look into this for you.

    Kind Regards,
    Michał

  • Hi benjamin405,

    It looks like your issue may be caused by incorrectly set TDD enablement delays. Can you share your TES profile, as well as any CSVs that it uses (e.g. auto-TDD timings, etc.)?
    Regarding the Tx_EN/Rx_EN overlap, I've tested this before and found that Tx_EN overlapping into Rx_EN by more than 5 us with minimal enablement delays resulted in the peak detectors malfunctioning. I therefore recommend that you do not overlap the Tx_EN/Rx_EN signals in TDD mode.

    Kind Regards,
    Michał

  • hi.

    Thanks for your reply. I will send you the information you mentioned.

    As a further note, I am not using Auto-TDD mode. Timing-related signals are generated by the FPGA.

     

    Since the timing signal is generated by the FPGA, the “TDD Enablement Delays” parameter in TES was used without change.
    -When controlling in FPGA, should Enable be turned ON 8000nS before the signal considering Rise-to-On Delay?




    attachment:

    TES Profile

    (TES 0.24.01)

    Many thanks.
  • Hi benjamin405, 

    I have no way to evaluate your timing without the Auto-TDD timing settings. Can you re-create your settings in the Auto-TDD interface in the TES?

    As for your question, yes. There should be a timing diagram to the right of those settings in the TES, and there is additional information in the ADRV9002 System Development User Guide that explain what each of these timing parameters means.

    Kind Regards,
    Michał

  • hi M_Bugajski,

    My reply was late because I needed to study the program to create a TES profile.
    We created an Auto TDD profile that is similar, but not exactly, to the timings we use. Please refer to the attached file.
    However, in EVB, I did not see the abnormal symptom of RX Data disappearing when running the attached Auto TDD.
    Where should I check on the board I'm using?
    As for RX SSI, I understand that ADRV9002 transmits signals to the FPGA.
    If RX Enable operates normally, what are the causes of the signal disappearing?

    attachment:

    TES / Automated TDD set file

    Kind Regards,

    benjamin405

  • Hi benjamin405,

    If the problem doesn't occur in the TES, then the issues is most likely with your own setup. You mentioned that there are differences in the timing between the TES Auto-TDD that you've created, and your own set up - it may be worth looking into those differences to see if they're the cause of this issue.

    Additionally, I suggest that you try using the SSI loopback to determine whether the issue is rooted in the RF side or the SSI side.

    Kind Regards,
    Michał

  • hi M_Bugajski,

    Thanks to your help, the problem has been resolved.
    The cause of the problem was Tracking Calibration.
    The frame length of the 5GNR signal we use is up to 1ms and as small as 250uS.
    When we generate sample code in TES, we do not use TES Auto-TDD but run TES Transmit and TES Receive individually.
    I chose to generate and use the code.
    At that time I selected all available items for TES Tracking Cals
    However, after setting up Auto TDD, I checked Tracking Cals and found that some items were disabled.
    After creating the disabled sample code and testing it by applying it to our board, the RX Data abnormality disappeared.

    After checking the User Guide, I was able to confirm the above information.

    Additional questions:

    1. How do I correct the disabled part? For example, after a certain period of time, Initial Calibrations proceed.

    2. If Tx digital pre distortion is disabled under 1ms, does the DPD function not work?

     

    Kind Regards,

    benjamin405

  • hi M_Bugajski,

    I look forward to hearing from you.

    Kind Regards,

    benjamin405

  • Hi benjamin405,

    1. There is currently a known issue regarding the scheduling of tracking calibrations, but I can't say when this will be resolved.

    2. For frame lengths under 1 ms, the tracking part of the DPD algorithm is disabled. This means that the ADRV9002 will calculate DPD coefficients during the initial calibrations, but will not be able to update them to track changes in environmental conditions.

    Kind Regards,
    Michał