Hello,
I'd like to use only tx1 and rx2 channels (or tx2 and rx1) in my custom board and so I want to know whether may I configure datarate of tx1 and rx2 channels seperately or not. As far as I know, i can do this easly but I'd like to confirm it since we'll make a custom pcb.
Regards
Hi musozc,
The datarates are not fully channel independent, as ultimately they must be divided down from the same system clock. If you'd like to check whether your setup is possible, I highly recommend that you download the Transceiver Evaluation Software for the ADRV9002, use it in demo mode, and set up your desired profile. These lights should then change to indicate whether your profile is valid (green) or invalid (red):
I hope that this answers your question.
Kind Regards,
Michał
Hi Mustafa,
That is not correct. I will look into getting that corrected. What they have described is an alternative use case. By default, the Tx SSI reference clock is not derived from the Rx.
The default behaviour (as is enabled in the TES, and as the ADRV9002 Eval Board is configured) is that Tx SSI has its own reference clock, separate from the Rx SSI reference clock. Those Tx SSI reference clock pins share their functionality with DGPIO_12 and DGPIO_13 for Tx1, and DGPIO_14 and DGPIO_15 for Tx2. However, on the Eval Board these DGPIOs are disconnected in favour or the reference clock.
However, there is an option to use the Rx SSI reference clock for the Tx. Doing so simplifies the SSI, and frees up the Tx SSI reference clock pins to be used as DGPIOs, but at the expense of configurability, which is what they mentioned. This requires changes:
1. Change the Tx SSI Reference clock source in the Profile Settings in the TES (in the Board Configuration tab) - This changes Tx SSI reference clock source to Rx.
2. And (optionally) to enable the DGPIOs, change the 0R connections on the Eval Board to disconnect the Tx SSI and connect the DGPIOs - This is required to use those pins as DGPIOs.
If by "reference design", they're referring to the Eval Board, then their statement that "There are some constraints with the loaded profiles due to the architecture of the reference design" is incorrect, because the reference design must be modified for the constraints to be due to design.
I hope that clears up any confusion.
Kind Regards,
Michał
Hi Mustafa,
That is not correct. I will look into getting that corrected. What they have described is an alternative use case. By default, the Tx SSI reference clock is not derived from the Rx.
The default behaviour (as is enabled in the TES, and as the ADRV9002 Eval Board is configured) is that Tx SSI has its own reference clock, separate from the Rx SSI reference clock. Those Tx SSI reference clock pins share their functionality with DGPIO_12 and DGPIO_13 for Tx1, and DGPIO_14 and DGPIO_15 for Tx2. However, on the Eval Board these DGPIOs are disconnected in favour or the reference clock.
However, there is an option to use the Rx SSI reference clock for the Tx. Doing so simplifies the SSI, and frees up the Tx SSI reference clock pins to be used as DGPIOs, but at the expense of configurability, which is what they mentioned. This requires changes:
1. Change the Tx SSI Reference clock source in the Profile Settings in the TES (in the Board Configuration tab) - This changes Tx SSI reference clock source to Rx.
2. And (optionally) to enable the DGPIOs, change the 0R connections on the Eval Board to disconnect the Tx SSI and connect the DGPIOs - This is required to use those pins as DGPIOs.
If by "reference design", they're referring to the Eval Board, then their statement that "There are some constraints with the loaded profiles due to the architecture of the reference design" is incorrect, because the reference design must be modified for the constraints to be due to design.
I hope that clears up any confusion.
Kind Regards,
Michał
Hi M_Bugajski ,
In order to work synchronosly FPGA and ADRV9002, we provide a ref clock to the FPGA, which is defined your "DEVICE CLOCK/MCS DISTRIBUTION" document (schematic document, sheet 6). Is it not enough?
Regards,
Mustafa
As far as I understand from the user guide, these pins (TX1_DCLK_OUT±) are required when we use Rx and Tx in different data rate, otherwise we could not connect them.
There is no data error/loss between the FPGA and ADRV9002 when we control transmitter output.
Regards,
Mustafa
The kernel process
I will recive this error on [5.507898]
"TX1 cannot be enabled while RX 1 is disabled."
So how to solve this problem.Linux drivers reject the profile which that TX1 and RX2 enabled version.
How can solve this problem ?
