ADRV9003
Production
The ADRV9003 is a highly integrated RF transceiver that has a single-channel transmitter, dual-channel receivers, integrated synthesizers, and digital...
Datasheet
ADRV9003 on Analog.com
ADRV9002
Recommended for New Designs
The ADRV9002 is a highly integrated RF transceiver that has dual-channel transmitters, dual-channel receivers, integrated synthesizers, and digital signal...
Datasheet
ADRV9002 on Analog.com
Hi,
What configurations should be set to achieve max output power (7.3 dBm as in datasheet)?
Can you provide an example data as it is given in No-Os build --> no-OS/axi_dac_core.c at master · analogdevicesinc/no-OS · GitHub
The max I am able to output is around -7dBm. (Including tx_output_boost enabled)
Best Regards
Hi,
I'll answer this from the TES point of view. This can also be achieved through API, please let me know if it's not clear which APIs to use.
Firstly, I'm setting my TES up for a generic DMR use case. Then there's three main things you can do to achieve max output power.
1) In the 'Radio' tab under 'Transmit Characteristics' enable "Optional 3dB full-scale output power boost"

2) In the 'Transmit' window, set the 'Tx Attenuation' to 0 dB
3) In the 'Data Source', set the Tone amplitude to be -1 dBFS

When I do this, I can achieve approximately the max specified power.

Best Regards,
Conrad
Hi,
It seems we are encountering with this problem again. The output power is measured as -4dBm and it changes with use of different sampling rates/profiles. We are using the provided sine lut table
Can you provide an example data as it is given in No-Os build --> no-OS/axi_dac_core.c at master · analogdevicesinc/no-OS · GitHub
as I mentioned here.
Is there anything we should take into consideration about the data? How can we manage to get full-scale with different profiles having different sampling rates?
Also could this be related to SSI delays? We implemented a Delay Block on FPGA side since the block in Adrv9001 was not enough. We are using the optimal delay configuration obtained by using the Interface Test Function provided in API.
In short:
Best regards
Hi,
In this case, it is likely an issue with your SSI. It may be related to delays or timing on the SSI path.
To determine this, use ADRV9002's internal tone generation to send a signal and observe it. In this case, the signal will not be sent across the SSI path so it will help to determine if this is causing the issue. Is the power output at the expected level in this case?
If it is then the issue is likely with your SSI. In this case, enable the Rx to Tx datapath loopback in ADRV9002. This will loop back the Tx data to the Rx which can be captured by your FPGA. You can compare the sent and received data to see if it is as expected.
I think it is likely that your SSI data is somehow misaligned and the MSB is not being sampled correctly. This would result in reduced power as you are seeing.
Best Regards,
Conrad
Hi,
In this case, it is likely an issue with your SSI. It may be related to delays or timing on the SSI path.
To determine this, use ADRV9002's internal tone generation to send a signal and observe it. In this case, the signal will not be sent across the SSI path so it will help to determine if this is causing the issue. Is the power output at the expected level in this case?
If it is then the issue is likely with your SSI. In this case, enable the Rx to Tx datapath loopback in ADRV9002. This will loop back the Tx data to the Rx which can be captured by your FPGA. You can compare the sent and received data to see if it is as expected.
I think it is likely that your SSI data is somehow misaligned and the MSB is not being sampled correctly. This would result in reduced power as you are seeing.
Best Regards,
Conrad
Hi,
With use of Internal Tone Generation the observed output power is
So the output power level is approximately 6dBm lower than expected
Kind Regards
Hi,
In this case, the issue is not with SSI since the data from the internal tone generator will not have been sent over SSI.
Firstly, ensure that your Tx Attenuation is set to 0 as above:

If this is correct, then the issue likely comes from your front end hardware. Is this same issue occurring across multiple boards and has this worked correctly previously?
I suggest checking the voltages across each side of your balun. Also check your front end design to see if there any errors that could be causing this attenuation.
Best Regards,
Conrad