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ADRV9002 RF Synthesizer setup

I have a question regarding the 2 RF Synthesizers in the ADRV9002 for which there is not sufficient detail in the datasheet nor the ADRV9001 System Development User Guide.

There is only mention that this is a fractional-N synthesiser with no detail on the resolution of the fraction. In addition there is also no detail on the limits of the reference frequency at the phase detector input nor on the reference divider divide range if any divider is used.

I have an application that I do not intent to run from a 38,4MHz device clock, but my own custom clock, but there is insufficient details in the above mentioned documentation to ascertain my design will work as intended. I need to verify that I can achieve my channel spacing too with my custom clock.

Can info be provided with some more basic details on the RF Synthesizers so as to ensure that I can achieve for what I need in my final application.

A similar situation arises for the Clock Synthesizer that ultimately determines the sampling rate.

Thank you.

  • Hello Thomas,

    If there's any extra detail you can provide (without giving away confidential info) on your application, that could help us to understand why the detail we provide is not sufficient for you. By and large, if ever we don't provide info about this product, it's because it's not info a designer needs in order to integrate our product into their design.

    Let's start with the reference Clk and build from there, most every other concern will be answered along the way. There is no requirement to run this transceiver at the 38.4MHz clk signal that we default to. Our Eval Board has an on-board VCTCXO that runs at 38.4MHz, hence our TES software defaults to using this frequency. However, as stated in the datasheet under Table 3, the device accepts reference clks anywhere in the range of 10MHz to 1GHz, with a voltage rating of 0.2Vp-p to 1Vp-p. There is a divider on the path from the Ref Clk to the Clk PLL, however it can be set to divide by 1 at the cost of worse noise performance. It can also be set much higher for better noise performance, at the cost of reduced System Clk, and thereby slower device operation.

    Now for the RF Synthesizers. We do not provide details on the resolution of the fractional divider because for the most part customers don't need to know this information. Our RF PLLs offer a tuning range of 30MHz to 6GHz, the divider values themselves are set via our APIs. When the Ref Clk value is provided to our APIs, and the Ref Clk divider is set, our Clk PLL can adjust the system Clk frequency very slightly in order to accommodate the Arbitrary Sample Rate functionality we provide for our data ports. After this adjustment is complete, the system Clk frequency is set, and our APIs can go about configuring the RF PLLs to deliver the carrier frequency desired given the system Clk.

    Our in-chip RF PLLs provide very good performance, with decent power and phase-noise. However if better noise performance is needed, there are a few additional features you could make use of. For example, an External LO with better phase noise performance could be used to replace our in-chip RF PLLs, at the expense of potentially greater power consumption and a larger space requirement. Perhaps of greater interest for you is our list of Calibrations. The ADRV9001 family comes with a suite of in-built initialization and tracking calibrations, including Digital Pre Distortion for the ADRV9002, to help minimize the device's noise during operation.

    The long in short of it is: if you can tell us what your channel spacing requirements are, and what you specific use-case for the ADRV9001 device is, then we may be able to tell you if our device is in spec for you. Given that this is a Software Defined Radio, with an enormous amount of configurability, characterizing the device for every possible use-case is simply an impossible task. We have provided all the information that the average customer needs to get their setups off the ground, however that does mean that more specific use-cases (such as yours) will have to do some digging to get the info they need.

    As I said, if you can provide us with more details for your use case, I will be happy to assist you further. At face value, the info you have asked for is not info we provide, because even if you had it these values wouldn't help your design efforts.

    I do hope to hear from you again soon!

    Best Regards,

  • Hello Oisin,

    Thanks for replying, however it does not answer my questions so that I can proceed. Also I do not have insight into the API's that you mention (unless I look at the wrong places). I will give more project details and see if this will help you in understanding why I am asking all of these questions, and in return get the details as originally requested.

    The project is more for the professional market and not for the commercial marked, hence mainline defaults of the SDR chip might not apply. As you can deduce, the volume of ADRV9002's that will be used for this project will be in the 100's at most and not in the 1000's. Development will be very specific to a special market segment. One of the areas we want to cover is the ATC Airband, i.e. 118MHz to 137MHz with a 8,333 kHz channel spacing. This is not the only area of intended use. Another requirement is SSB (Single Side Band) - typically USB in the UHF band. This will be normal voice/speech channels .i.e. 3kHz Bandwidth channels on a channel spacing of 12,5 kHz. Obviously some fine tuning mechanism for the receiver will be required to combat slight frequency errors between transceivers. Therefore I need a 4,1666 kHz "raster" on the RF PLL as 4,166 kHz will be a common raster that will accommodate both 8,333 kHz as well as 12,5 kHz channel spacing.

    In addition, I would like to use a high performance DXCO that we have stock-pilled on on another project and not need to introduce a new DCXO which would come with a new hassle of MOQ and bad price breaks due to low quantity, hence for me wanting to break away from the default/recommended 38,4 MHz. Currently we have plenty of 80,000 MHz DCXOs in our inventory and would like to use this for the reference clock.

    Lastly Page 12 of the ADRV9002 datasheet mentions a 4,5 Hz channel spacing from a 38,4 MHz reference clock, but following the calculation, I get something closer to 4,577 Hz. Firstly, this is a very fine channel spacing, requiring lots of multiplication to get to UHF frequencies, typically resulting in bad phase noise when high "multiplication" values are used and secondly, hopefully the API's use the exact value and not any rounding as multiplying up to UHF can result in significant frequency errors, especially when using SSB on a relative small channel spacing.

    Sorry for the delayed response, our company was closed down for a lengthy Christmas period, like many other companies in the southern hemisphere, as we enjoy our summer break/holidays in December.

  • Hello again ThomasFunk,

    I must apologise for the long delay also, we only just returned from our Christmas break as well, however I took some extended holidays. I do hope you had a great start to your 2022!

    On the face of it, your application does seem to be one we can accommodate. The Clk you described sounds fine as far as the ADRV9001 products are concerned, you should see minimal issues with using this Clk source provided it is sufficiently clean of noise.

    As for you channel spacing requirements, to the best of my knowledge you shouldn't see any issues when using our part, however to confirm this I will bring your application to our team and discuss it with them. With any luck I'll have more information available for you by the end of next week. 

    Depending on how further discussion go on this topic, we may update the User Guide based on your feedback. More on that once we get you sorted out.

    I'll be in touch again soon!
    Best Regards,

  • Hello ThomasFunk,

    I brought your concerns to the team, this is what our Signal Chain specialist said in response:

    The ADRV9002 RF transceiver was designed for the many mission critical comminutions markets, like emergency services, utility services, government and military tactical radio systems, and so on.  So ADRV9002 definitely can support your application.

    Both Clock PLL and RF PLL is based on fractional_N architecture, the modulus is  2^23 - 15

    The reference clock divider for RF PLL is always 1 if DEV_CLK <307.2Mhz ,  typical frequency step can be calculated by DEV_CLK / (2^23-15)  (Datasheet) , considering the LO Generator Divider after the VCO, the frequency resolution would be at least ½ of this typical number.

    They went on to note:

    I found I have already updated the following for all 3 data sheets:

    For 38.4 MHz DEV_CLK, use the equation DEV_CLK/((2^23 − 15)×2) to calculate, assuming the LO divider is 2

    This is based on the previous discussion and I hope it is correct. It will be included into the next version.

    So it seems that some of your concerns are to be addressed in upcoming versions of our documentation. I do hope this extra detail provides some clarity for you. Let me know if you have any further questions.

    Best Regards,

  • Hello Oisin,

    Thank you for the speedy reply and bringing it to the team, appreciated.

    It sheds a bit more light, but still not to the extend I was hoping for.

    I have enough confidence that the chip will work with my 80 MHz reference, and giving me my channel spacing, but for completeness and consistency sake, I feel the datasheet and users guide needs an update beyond what you mentioned in your last answer.

    I'll explain the inconsistency I have picked up: The datasheet on Page 12 mentions DevClk/(2^23-15), whereas the user guide gives the value 8388473 which equates to DevClk/(2^23-135). But even this value would not give the claimed exact raster of 5 kHz as stated on page 96 of the Users guide in my opinion. According to my calculations, to get an exact 5 kHz raster of valid multiples of 38,4 HZ, the Modulus needs to be 2^23 - 2048 i.e. the modules needs to be 8386560 with an accompanying fractional value of 1092. Can you or the team or the Signal chain Specialist confirm this please.

    It is mentioned that the Modulus value is programmable, is this really the case and if so what would its maximum programmable value be (2^23 or 2^23 -1 or 2^24 or 2^24 -1 or some other value that I did not mention) ?

    It is quite likely that the PLL sub-section is based on an existing loose standing PLL chip like for example the ADF4155 (as an example), if so, on which chip is it based and perhaps a cross reference in the updated Users Guide should also suffice instead of updating the Users Guide with all the fine detail, then you won't need to repeat all the fine detail nor clutter the Users Guide with info that most users won't be interested in, but still provide enough for the few users that would like to understand the flexibility of the ADRV9002 to the fullest.

    Best Regard


  • Hello Again,

    I just like to add-on to the previous answer the following ideas/comments: Looking at the ADRV9026 Users Guide (UG1727), I like to propose the idea of adding similar tables that it has for the PLL/Synthesizer to the ADRV9001 Users Guide too, referring in specific to Tables 56 and 57 on Page 75 of the ADRV9026 User Guide. There one can see in a glance on the frequency steps and channel spacing raster/s available as default. Using those, one can then easily recalculate frequency steps and rasters for custom clocks.

    Further, I am getting the impression that the fractional synthesizers integer and fractional values are calculated inside the ADRV9002 and not in the provided API's as frequency is passed from the API to the ADRV9002 as an 64 bit integer together with the NCO offset frequency. Can my observation be confirmed.

    Lastly, it is still somewhat unclear (as the user guide never explicitly states it nor pictures this via a block diagram), the reference clock to the LO PLL and System clock is taken from the raw DEV_CLK input and not after the  divider that feeds the DEV_CLK Out pin. Also what happen if the input clock is above 307.2MHz? Does the ADRV9002 automatically select a different divider or does this manually have to be set?



  • Hello Thomas,

    Your attention to detail in our documents is greatly appreciated! I have brought your feedback to the engineer responsible for this section of the User Guide and Datasheet. Once they have made a decision as to what to do next, I will return and inform you.

    I will do my best to answer some of your questions from the above replies:

    • For you calculations, I will return with the RF Synthesizer Specialist's response
    • For the max Modulus programmable value, again I will have to return with the specialist's response. I will say that it's not information that is ultimately useful for the user, as users cannot control this value anyway. Our APIs abstract a very large portion of those blocks away, meaning a user need only specify the Dev_Clk they want to use and the Carrier frequency they are interested in. After that, our APIs adjust the Clk PLL and the RF PLLs to suit the application. All a user must decide is whether the phase noise present in our system is acceptable.
    • The integer and fractional_n components are computed by the backend of our APIs. The results of these calculations are communicated with the device via the SPI interface. By and large the ARM is used to control device timing and manage the execution of calibrations.
    • I will double check regarding where the DEV_Clk for the RF PLLs comes from, but I believe the RF PLLs are supplied with the output of the DEV_Clk PLL and not the external reference.

    Best Regards,

  • The programable PLL modulus is from our PLL design perspective, but not for customers, ADRV9002 software only offers the default 8388593(2^23 -15), the UG description will be updated in the next version.  

  • The sole reference clock for ADRV9002 is "DEV_CLK_IN", all the internal PLLs (RF, Clock) are driven by this reference. 

    "DEV_CLK_IN" can be up to 1Ghz (LVDS mode), but RF PLL PFD is only up to 307.2Mhz. extra reference clock divider (/2,/4,/8/..)  will be applied if the DEV_CLK is bigger than 307.2Mhz.  ADRV9002 software takes care of this automatically with the "DEV_CLK" frequency input. 

  • Hi,

    Is there an approximate target date for when one can expect the updated UG and perhaps updated datasheet to be published?