adrv9002 axi_mspi clock period does not work with slow clocks

Hi,

Can you please elaborate what you mean by a clock period value of 1 or 2?
In the meantime, I will source some answers to your other questions.

Kind Regards,
Michał

The axi_mspi has a programmable spi clock frequency.
This is programmed by the sdk code in file adi_adrv9001_hal_linux_uio.c.

The file sets the clock period for the spi clock.

When the period value is a 1 or 2, the spi communicates with the adrv9002.

When the period is a larger value (for a slower spi clock), the spi communication with the adrv9002 fails.

From my calculations, a period value of 1 or 2 results in an spi clock that is too fast. (see previous msg).

I would like to have a slower clock to meet the part specifications, but it does not seem to work.

Hi,

For a 300 MHz AXILite clock, you'll need to set CLK_CNT > 2 to bring the clock speed within spec and satisfy the equation 150/(CLK_CNT+1). Running the SPI clock outside of spec might work in your current instance, but we cannot guarantee that it will continue to work over the range of advertised environmental conditions.

The interrupt is needed if you are using an ISR. It can be connected to the PSU/PS7 interrupt pins.

Kind Regards,
Michał

Thanks for the reply.

I am unable to find CLK_CNT.
Is this in the HDL or the SDK.
I did a grep on both and cannot find this.

Also, I set the axi lite clock back to 100MHz and tried to slow the clock down.
Again, the spi fails if the period that is written to AXI_MSPI_SCLK_PERIOD_ADDR (0X40) is not a value of 1 or 2.

Thanks 

Hello Michał,

Any word on where I can find CLK_CNT?

Thanks

Hi,

I believe REG_SSN_CLK_COUNT is the variable you're looking for. Give this a try and report back your progress.

Kind Regards,
Michał

Hello Michał,

There is not variable in the hdl or the sdk with the name REG_SSN_CLK_COUNT.

There is a register in the hdl called axilite_ssn_sclk_count.

And this can be read from the AXI_MSPI_SSN_SCLK_COUNT_ADDR (0x144). However, this is read only.

Any other thoughts?

Thanks

By any chance is there a time out that occurs if the spi is running slower?

Thanks

Hi,

The timeout issue is up to the software; all AXI peripherals have timer registers.

Going back to your original question, did you try measuring the the clock frequency with the period set to 2? Going back to the formula 150/(PERIOD+1), a period of 2 should bring you to an acceptable frequency. Have you tried changing the variable REG_SCLK_PERIOD?

I'll get back to you if I have any clarification on the issues caused by other clock periods.

Kind Regards,
Michał

Hello Michal,

Setting the variable REG_SCLK_PERIOD is what I am changing.

If this value is a 1 or a 2, then everything seems to work fine.

if the variable is set to a value of greater than 2, then it no longer works.

Where would I find the axi_mspi timeout in the sdk software?

I cannot seem to find this.

Thanks