ADRV9002_DEV CLKIN & TX Port Interface voltage level

Hi James, 

1. The max current for your nets will be different to our Eval board. We used a star connection for the supplies so that the current is dispersed through various different ferrit beads, as such we dont expect the full current to go through one single bead. The ferrite beads can absolutely be of a lower spec as long as it covers the max current on your net, this will be specific to your board. What kind of system are you building?

Im not entirely sure what the question is for the second part, we have a clk into the ADCLK944 and that supplies the clk for the ADRV9002.

2. 3. 4. The ADCLK944 takes in a sinusoid clk and produces the clk for the ADRV9002. The ADRV9002 can also accept a sinusoid clk input because there is an internal buffer. Ideally it takes a clipped sinusoid. The specs for these are in the Data Sheet (INTERNAL LO, EXTERNAL LO, AND DEVICE CLOCK section) 

5. the ADCLK944 output is LVPECL and using a resistor network outside the part we create the LVDS signal needed for the input to ADRV9002 

6. The 825mV - 1675mV is the common mode voltage range and the 254mV - 454mV range you mentioned is the differential voltage swing that sits on top of the common mode voltage. 

7. The common mode voltage is required for the LVDS signal. What is your intent here?

Hi,

Pls reply for the below queries.

Q1. As per trailing conversion If the ADRV9002 DEV CLKIN is accept the sinusoidal input, what is device clock interface mode XTAL or CMOS?

Q2. In our module, 4 nos of ADRV9002 chip is planning to use. So totally 4 channel fanout is required of devclk in. Due to the better phase noise requirement, we are planning to use the power divider instead of clock fanout buffer (ADCLK944) used in the EVM. Because fanout buffer will generate the additive jitter and power divider will not be.

Clock scheme will be OCXO (50 ohm o/p imp +Sinusoidal output)-> 4 ch o/p Power divider (0.8V output at each channel) -> 4 no of ADRV9002

Can u suggest this approach will get the better performance or not which means power divider fanout instead of LVDS fanout for the DEV CLKIN?. Because i have studied in the user guide as "Recommended approach is to use differential signalling for DEV_CLK clock"

Q3. In user guide Rev A, power supply recommendation is not available. Pls share If any preliminary data is available. Because the decoupling capacitor requirement is too high in the EVM module near 20 nos of 100uF, 24 nos of 1uF.

Regards

James A

Hi James, 

1) You can supply CMOS clk or an XTAL to the ADRV9002. They work in very similar ways. 

You just need to connect them as shown in the block diagram and give the appropriate voltage level to MODEA pin depending on which clk input you chose. 

2) We would suggest that you use LVDS clk input for an application like this to make sure that the clk signal is not disrupted. You will be looking for a configuration like this

Where the clocking block is at the top right. A suggested part for this would be the AD9528  that can provide the dual ended clk signals needed. 

3) We are currently working on power supply recommendations, we don't have any preliminary data available but will follow up when we do.  

Hi,

 I am planning to use ADCLK948BCPZ part for clock fan-out to FPGA and RF transceiver of ADRV9002 part with input clock source will be OCXO 10 to 100MHz range.

For ADCLK948BCPZ part, the phase noise details are given for 1Ghz range in the datasheet and phase noise difference in b/w clock source (500-06672) and fanout buffer with multiplier like below,
~1dB @ 100KHz
~2dB @ 1MHz
~3dB @ 1MHz
~6dB @ 10Mhz

1. In my case there is no multiplier in b/w the OCXO and fanout buffer. Can u provide the phase noise difference  in the range of 10 to 100MHz input clock range for fanout buffer and consider the input phase noise details as per in the datasheet (500-06672)?

2. Please provide the clock fanout buffer phase noise details w.r.t given 10MHz clock input OCXO phase noise  as per below,

OCXO phase noise (input)               ADCLK948BCPZ phase noise
    -105dBc @ 1Hz
    -135dBc @ 10Hz
    -157dBc @ 100Hz
    -167dBc @ 1000Hz    
    -172dBc @ 10KHz
    -173dBc @ 100KHz

Regards

James A

Hi James, 
For info on any of the clock parts search and post in the Clock and Timing forum on Engineer Zone. 

Also bear in mind the section in the UG for the ADRV9002 on the MCS (multi chip synchronization)  it should be useful for this system. 

Regards

Ruairí

HI,

Thanks for your reply. I ll post the query in Clock and timing forum.

Can i route the MCS signal from FPGA or should be from fanout buffer of  ADRV9002  dev clk in.

Thanks

James S