ADRV9002 DAC resolution

Hi HM,

To begin answering your question, I need to correct your second statement: The high-performance ADC is a 5-bit Continuous Time Delta Sigma ADC (CTDS ADC). The low-power ADC is a 16-bit Voltage Controlled Oscillator (VCO) architecture. 

As for the DACs, I'm assuming you mean the DACs present on the Tx datapath? These are 16-bits wide (Please review TRANSMITTER SIGNAL CHAIN - ANALOG FRONT END (AFE) - DAC in the user guide for more details), however there are also Auxiliary DACs/ADCs which are 12-bits wide (please review AUXILIARY CONVERTERS AND TEMPERATURE SENSOR in the user guide for more details)

Thanks,

Oisín.

If the high-performance ADC is a 5-bit Continuous Time Delta Sigma ADC (CTDS ADC), Then what will be typical SNR performance for the 40MHz Bandwidth?

Is it 5 bit or 16-bit? Pls confirm.

If the high-performance ADC is a 5-bit Continuous Time Delta Sigma ADC (CTDS ADC), Then what will be typical SNR performance for the 40MHz Bandwidth?

Is it 5 bit or 16-bit? Pls confirm.

Hi Sugu,

In the user guide under Rx/ORx Signal Chain - Receive Data Chain: Analog Front End there is a section dedicated to the ADC options. Here it describes each ADC option in more detail, but in answer to your question I can confirm that the HP ADC is a 5-bit CTDS ADC, the LP ADC is a 16-bit VCO ADC.

I don't have the exact data you're requesting, I'll look into it over the coming days. In the datasheet under Receiver Specifications there is a host of measurements going through Noise Figure, Image Rejection, etc. across center frequency. Let me know if this data answers your questions.

Regards,

Oisín.