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ADRV9002 DAC resolution


What is the resolution of  DAC of ADRV9002?

The high-performance ADC is 5bits, and low Σ-Δ ADC is 16bits described in UG-1828.



  • Hi HM,

    To begin answering your question, I need to correct your second statement: The high-performance ADC is a 5-bit Continuous Time Delta Sigma ADC (CTDS ADC). The low-power ADC is a 16-bit Voltage Controlled Oscillator (VCO) architecture. 

    As for the DACs, I'm assuming you mean the DACs present on the Tx datapath? These are 16-bits wide (Please review TRANSMITTER SIGNAL CHAIN - ANALOG FRONT END (AFE) - DAC in the user guide for more details), however there are also Auxiliary DACs/ADCs which are 12-bits wide (please review AUXILIARY CONVERTERS AND TEMPERATURE SENSOR in the user guide for more details)



  • Hi, Oisin,

    Thank you for your support.

    I understand the DAC resolution.

    I made a mistake in the description of ADC. Thank you for correcting it.

    I have another question.

    What kind of architecture is the VCO architecture of the LP ADC?



  • Hi HM,

    VCO based ADC's are a particular type of ADC which are designed to be highly digital in nature. This architecture is very useful for on-chip testing and integration into CMOS systems. VCOs themselves are a standard piece of electronics, they output a digital square wave whose frequency is a function of the input voltage. By comparing the output frequency to that of a separate clock reference using digital counters, one can create an all-digital ADC. These circuits are generally liked for their ability to implement simplified versions of high-order Sigma-Delta ADC's, which come with great noise characteristics and a very high dynamic range. Despite the LP ADC's on the ADRV9002 Rx datapath having slightly worse performance than the HP ADC's, you will note that they do have a very large dynamic range and great noise performance.

    Unfortunately I struggled to find an article on which discussed this circuitry, however a quick Google search returned numerous books, papers and articles which discuss this architecture in varying degrees of depth. Here's one block diagram I found of this architecture, available at the following link:

    I do hope this helps. Thanks very much for your interest.

    Best Regards,


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