This guide will detail the process for generating sample C99 code to perform a set of user defined tasks and then how to compile this code on the ZC706 FPGA platform. Successfully completing this step is crucial part in the process of designing and implementing your own custom platform for the ADRV9001.
Step 1: Configure and Program the Device
For this task any setup will work. Everything you do in TES saves the relevant API calls to a log file in the order you called them, so it’s advisable to rehearse your setup a few times before producing C99 code just to make sure you don’t include API calls that were mistakes. For this example, we’ll use an LTE setup in FDD mode.
Quite literally any configuration that programs and functions in your tests with TES will work for this. Set the Carries tab as your application requires, here we’ll simulate a high-frequency application using the 2A Evaluation Board (the 3GHz – 6GHz version):
And similarly, setup every other tab as your application requires. As long as you can press the “Program” button and have the part operate as expected when transmitting / receiving producing sample code will work. Once you’re ready, press “Program”.
Step 2: Go through your application
This step is rather unspecific, whatever it is your application requires the part do, do that. Every task you perform from here is recorded, so having rehearsed this part in detail will help avoid unnecessary API’s from being called. Go through your application, turn on and off the Tx / Rx, set and adjust the Tx Attenuation and the Rx Gain, step through a frequency hopping table, everything will be recorded. For this example, we’ll turn on the Tx, then the Rx, before switching off the Tx and then the Rx.
If you’re so inclined you can verify your Tx output and Rx config using a spectrum analyser and a signal generator respectively, however this verification should have been completed well in advance of starting this guide.
Once finished, be certain the stop any RF activity (Tx or Rx). For best results when generating code, it’s recommended to be in the Primed state. If you’re in any doubt about what state you’re in, press View -> Radio State
These radio buttons re interactable, so if anything is in a state which is not Primed, simply press the Primed button for that channel. Bear in mind again, anything you do here will be saved to the log file and, thus, to the generated C99 code.
Step 3: Generate Code
Simply press Sample Code -> {Language of Choice}. You can of course choose whichever language you plan to develop your application in, for this example we’ll use C99.
Feel free to inspect the code here. Most of it will make sense just from reading, certain files (like initialize.c) are a bit more obscure. For the time being however do not edit these files. When you’re developing your own HAL and pushing to your own custom platform these files will need editing, but for now they should remain exactly as they are.
Step 4: Copy Source Code to FPGA
Press the Disconnect button in TES, being certain to leave the FPGA powered on with the ethernet cable connected. Navigate to the folder where the Analog Devices SDK is installed. If all defaults were selected during installation it should be in: C:\Program Files (x86)\Analog Devices\adrv9001-sdk. From there go into \pkg\production. From this folder we can upload generated C code to the FPGA platform, and to our own custom platform further down the line.
*Note: The “test1” folder shown here will not be in your directory by default. Add it now. Copy the code from your Sample Code folder and paste it into test1. This folder can be named anything you want, but “test1” is the name expected by our software tool.
The python file “compile_on_platform.py” is what we’ll use to copy our source code to the FPGA. We’ll need a Python 2.7 interpreter and the paramiko module installed. Be certain to read the “README.md” file in this folder to understand the requirements for running this python file. Run this file however you find best, here we’ll use a Windows terminal to call the Python interpreter.
*Note: If you have compiled any code to the FPGA before you must remove it before compiling new code, as not doing so will cause versioning errors at compile time. Use PuTTY to log in to the FPGA via SSH (shown in more detail in Step 5) and do the following before proceeding:
For the FPGA platform all default values will be acceptable. For your own custom platform, you will need to adjust the connection info.
Step 5: Compile and Run your Code
Login via PuTTY as specified in the User Guide: (username: root, password: analog)
Navigate the folder structure as shown:
Now simply call “make” and let it compile. If any bugs appear, you will have to track down the cause of the issue and correct it manually.
Once compiling has completed successfully the test1 folder will have some new files in it, most notably is an executable called “example”:
This executable will perform exactly the same tasks you outlined in TES at the beginning of this guide, only quicker. Simply type “./example” and allow it to run. Monitor your Tx output (if you programmed one into this body of code) to verify that it has run as expected:
At this point we have successfully generated C99 code to handle a specific use-case and compiled it onto our host ZC706 platform.