Q&A - Recent Threads

AD9371 + ZU15EG: Intermittent SYSREF Alignment Error Despite Integer LMFC/SYSREF Relationship

UVLSIDRIVER — Fri, 19 Jun 2026 12:22:04 GMT

Hello ,

I am working on a custom AD9371 + ZU15EG design and am seeing the "SYSREF Alignment Error = Yes" status intermittently after some power cycles. Most power-ons work correctly, but occasionally the alignment error is reported.
Iam using reference project HDL and NO OS project provided in ADI github.

I reviewed the ADI JESD troubleshooting documentation and found two possible causes:

SYSREF frequency is not an integer multiple/submultiple of the LMFC frequency
SYSREF violating setup/hold timing with respect to the JESD device clock

For our configuration:

Lane rate = 2457.6 Mbps
F = 2 octets/frame
K = 32 frames/multiframe
LMFC frequency = 3.84 MHz
SYSREF frequency = 0.96 MHz

Since SYSREF = LMFC/4, the first condition appears to be satisfied.

Regarding the second point, the troubleshooting guide suggests constraining the SYSREF path relative to the device clock. We would like to investigate this further.

Our clocking setup is as follows:

HMC7044 generates both clocks and SYSREF.
Clock and SYSREF traces are length matched on the PCB.
AD9371 reference clock = 122.88 MHz.
We are using the standard 61.44 MHz profile configuration files from the ADI reference design.
In the HDL reference design, the JESD device clock is generated by a Clock Wizard whose input is the GT Channel 0 output clock, and the Clock Wizard output is used as the device clock for the JESD IP.

My questions are:

In this architecture, what clock should be used as the timing reference when constraining the SYSREF path?
How should the SYSREF path be constrained in Vivado?
Has anyone observed intermittent SYSREF alignment errors in a similar AD9371 setup despite having matched clock/SYSREF routing?
Besides SYSREF frequency relationship and setup/hold timing, are there any other common causes that could lead to intermittent SYSREF alignment errors across power cycles?

Any guidance or recommendations would be greatly appreciated. Thanks.

AD9375 TX1 and TX2 impedance matching Network in band 300 to 1000Mhz

alexisdupont1994 — Mon, 11 May 2026 19:59:08 GMT

Hi,

we are planing to use the AD9375 in the frequency band of 300 to 1000Mhz. From the UG-992 p.252 , we have to use the following components for the following circuit (See images below).

So, we have to use the B0322J5050AHF. From the component, it seems that L305 must be added, however, the conversation at this link tells that the L305 is DNI:

https://ez.analog.com/rf/wide-band-rf-transceivers/design-support-ad9371/f/q-a/575671/b0322j5050ahf-for-ad9371-s-tx-port

I am a little confuse by that answer, so i just want to validate if i have to put L305 between Pin 2 and Pin 3, but not to pin 4?

Thank you very much and have a nive day!

Deframer error 0x61

tchrist — Mon, 30 Mar 2026 08:20:04 GMT

Hello,

We are having trouble with the deframer/tx path using the AD9371 - getting the error code 0x61, 0x21 etc having the "frame symbol lost" as the common denominator.

We can close to consequently reproduce the error by resetting the FPGA and then running the initialization for the JESD204B link. Additionally, we see "BADDISP" when reading "MYKONOS_deframerGetIrq". Based on the readouts, we can see that it fluctuate between CGS and ILAS phase, not reaching the DATA state.

Adding a debug core (ILA-core) to some of the signals reveal some weird behavior during the 2 deframer errors. Especially, the ilas_config_data is all 0's for the 2 errors - what might be the cause of this?

Waveform of working link:

Waveform with deframer error 0x61 (notice how the data is first sent on the second multiframe after sync?):

Waveform with deframer error 0x21 (notice the sync deassertion during the ILAS phase):

Additionally, the SYNC signal falls close to the LMFC boundary in all 3 waveforms, which in our understanding should fall somewhat in the middle of a LMF. This can controlled via the LMFC_offset, right?

We are using Vivado 2022.2 and ADI-HDL version 2022_r2:

7ea497b6c24172ee293d6e0a9a387a16973da5ce 2022_R2 https://github.com/analogdevicesinc/hdl/tree/2022_R2

Hope you can give some much needed insight into the HDL and the problem.

Thanks in advance,

Thomas

Clock definition

HenryIII — Thu, 26 Feb 2026 13:03:15 GMT

Hello,

I would like to configure ad9375 with a different sampling frequency on Tx such as 60 MHz using a different clock from 30.72 MHZ, but when I charge the configuration file it gives error on JESD clock.

Is it possible to configure the AD9375 with a different multiple clock?

Or is there any EVB of9375 with different clock definition?

Thanks and Best regards

Ad9371 Saturation on TX when sending IQ with high PAPR

Jawad — Sat, 21 Feb 2026 14:25:54 GMT

I am using Radioverse AD9371_Software.exe to generate Mykonos files for the AD9371.

Or when transmitting signal with high modulation scheme (i.e., high PAPR) than the sinewave I am observing saturation on the TX output.

I am suspecting the saturation on the TX FIR filters.

Kindly can you share the configuration file (derived from the one attaced herein) to be able to transmit 100 MHz 5G signal bandwidth without saturation ? I am expecting to have 12 dB PAPR while the sinewave have 3 dB of PAPR.

ez.analog.com/.../2024_5F00_11_5F00_14_5F00_AD9371_5F00_CFG_5F00_1Tx1Rx_5F00_100M.txt

ARM Mailbox Busy – Command not executed in MYKONOS_sendArmCommand() during initialization

PUJ — Tue, 17 Feb 2026 07:06:46 GMT

Hi,

I am using ZCU102 (Ultrascale+) with AD9371 (Mykonos) and encountering the following error during initialization.

I have attached the TES-generated profile code and the initialization configuration files used for this setup for review.

Vitis Error Log Output

Please wait...
rx_clkgen: MMCM-PLL locked (76800000 Hz)
tx_clkgen: MMCM-PLL locked (153600000 Hz)
rx_os_clkgen: MMCM-PLL locked (153600000 Hz)
MCS successful
CLKPLL locked
ARM Mailbox Busy. Command not executed in MYKONOS_sendArmCommand()

Questions

What conditions cause the ARM mailbox to remain busy?
Does this indicate that the ARM firmware is not running correctly?
Which debug registers should be checked before issuing ARM commands?
Is there any mistake in my attached profiles?

Any suggestions or debug guidance would be greatly appreciated.

Thanks

myk.c

/**
 * \brief Contains init setting structure declarations for the _instance API
 *
 * The top level structure mykonosDevice_t mykDevice uses keyword
 * extern to allow the application layer main() to have visibility
 * to these settings.
 * 
 * All data structures required for operation have been initialized with values which reflect these settings:
 * 
 * Device Clock:
 * 122.88MHz
 * 
 * Profiles:
 * Rx 100MHz, IQrate 153.6MSPS, Dec5
 * Tx 100/250MHz, IQrate 307.2MSPS, Dec5
 * ORX 240MHz, IQrate 307.2MSPS, Dec5
 * SRx 20MHz, IQrate 38.4MSPS, Dec5
 * 
 */

/**
  \page Disclaimer Legal Disclaimer
  Copyright 2015-2017 Analog Devices Inc.
  Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
 */

#include <stddef.h>
#include "t_mykonos.h"
#include "t_mykonos_gpio.h"
#include "myk.h"

static int16_t txFirCoefs[] = {-16,34,-95,215,-475,1136,-3455,22121,-4794,2304,-899,393,-177,76,-31,19};

static mykonosFir_t txFir =
{
    6,              /* Filter gain in dB*/
    16,             /* Number of coefficients in the FIR filter*/
    &txFirCoefs[0]  /* A pointer to an array of filter coefficients*/
};

static int16_t rxFirCoefs[] = {-16,-22,18,74,24,-132,-152,132,372,38,-598,-474,638,1178,-206,-1952,-984,2362,3152,-1612,-6544,-2164,12806,26836,26836,12806,-2164,-6544,-1612,3152,2362,-984,-1952,-206,1178,638,-474,-598,38,372,132,-152,-132,24,74,18,-22,-16};

static mykonosFir_t rxFir =
{
    -6,             /* Filter gain in dB*/
    48,             /* Number of coefficients in the FIR filter*/
    &rxFirCoefs[0]  /* A pointer to an array of filter coefficients*/
};

static int16_t obsrxFirCoefs[] = {-32,136,-348,747,-1404,2412,-3827,5730,-8371,10473,-13745,24655,27364,-16650,10146,-7384,4611,-2790,1593,-830,384,-148,43,0};
static mykonosFir_t obsrxFir =
{
    0,              /* Filter gain in dB*/
    24,             /* Number of coefficients in the FIR filter*/
    &obsrxFirCoefs[0]/* A pointer to an array of filter coefficients*/
};

static int16_t snifferFirCoefs[] = {10,31,59,71,30,-92,-283,-456,-466,-175,440,1192,1683,1444,198,-1871,-3988,-4942,-3512,958,8118,16519,23993,28395,28395,23993,16519,8118,958,-3512,-4942,-3988,-1871,198,1444,1683,1192,440,-175,-466,-456,-283,-92,30,71,59,31,10};
static mykonosFir_t snifferRxFir=
{
    -12,            /* Filter gain in dB*/
    48,             /* Number of coefficients in the FIR filter*/
    &snifferFirCoefs[0]/* A pointer to an array of filter coefficients*/
};

static mykonosJesd204bFramerConfig_t rxFramer =
{
    0,              /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15)*/
    0,              /* JESD204B Configuration Device ID - link identification number. (Valid 0..255)*/
    0,              /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31)*/
    2,              /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain*/
    32,             /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes)*/
    1,              /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled.*/
    1,              /* 0=use internal SYSREF, 1= use external SYSREF*/
    0x03,           /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled*/
    0x04,           /* serializerLaneCrossbar*/
    22,             /* serializerAmplitude - default 22 (valid (0-31)*/
    4,              /* preEmphasis - < default 4 (valid 0 - 7)*/
    0,              /* invertLanePolarity - default 0 ([0] will invert lane [0], bit1 will invert lane1)*/
    0,              /* lmfcOffset - LMFC_Offset offset value for deterministic latency setting*/
    0,              /* Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, 0 = not set*/
    0,              /* Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set*/
    0,              /* Selects SYNCb input source. Where, 0 = use RXSYNCB for this framer, 1 = use OBSRX_SYNCB for this framer*/
    0,              /* Flag for determining if CMOS mode for RX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS*/
    0,              /* Selects framer bit repeat or oversampling mode for lane rate matching. Where, 0 = bitRepeat mode (changes effective lanerate), 1 = overSample (maintains same lane rate between ObsRx framer and Rx framer and oversamples the ADC samples)*/
    0               /* Flag for determining if API will calculate the appropriate settings for framer lane outputs to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in serializerLaneCrossbar will be used*/
};

static mykonosJesd204bFramerConfig_t obsRxFramer =
{
    0,              /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15)*/
    0,              /* JESD204B Configuration Device ID - link identification number. (Valid 0..255)*/
    0,              /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31)*/
    2,              /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain*/
    32,             /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes)*/
    1,              /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled.*/
    1,              /* 0=use internal SYSREF, 1= use external SYSREF*/
    0x0C,           /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled*/
    0x40,           /* Lane crossbar to map framer lane outputs to physical lanes*/
    22,             /* serializerAmplitude - default 22 (valid (0-31)*/
    4,              /* preEmphasis - < default 4 (valid 0 - 7)*/
    0,              /* invertLanePolarity - default 0 ([0] will invert lane [0], bit1 will invert lane1)*/
    0,              /* lmfcOffset - LMFC_Offset offset value for deterministic latency setting*/
    0,              /* Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, 0 = not set*/
    0,              /* Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set*/
    1,              /* Selects SYNCb input source. Where, 0 = use RXSYNCB for this framer, 1 = use OBSRX_SYNCB for this framer*/
    0,              /* Flag for determining if CMOS mode for RX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS*/
    1,              /* Selects framer bit repeat or oversampling mode for lane rate matching. Where, 0 = bitRepeat mode (changes effective lanerate), 1 = overSample (maintains same lane rate between ObsRx framer and Rx framer and oversamples the ADC samples)*/
    0               /* Flag for determining if API will calculate the appropriate settings for framer lane outputs to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in serializerLaneCrossbar will be used*/
};

static mykonosJesd204bDeframerConfig_t deframer =
{
    0,              /* bankId extension to Device ID (Valid 0..15)*/
    0,              /* deviceId  link identification number. (Valid 0..255)*/
    0,              /* lane0Id Lane0 ID. (Valid 0..31)*/
    2,              /* M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
    32,             /* K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes)*/
    1,              /* scramble  scrambling off if scramble= 0.*/
    1,              /* External SYSREF select. 0 = use internal SYSREF, 1 = external SYSREF*/
    0x03,           /* Deserializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */
    0x04,           /* Lane crossbar to map physical lanes to deframer lane inputs [1:0] = Deframer Input 0 Lane section, [3:2] = Deframer Input 1 lane select, etc */
    1,              /* Equalizer setting. Applied to all deserializer lanes. Range is 0..4*/
    0,              /* PN inversion per each lane.  bit[0] = 1 Invert PN of Lane 0, bit[1] = Invert PN of Lane 1, etc).*/
    0,              /* LMFC_Offset offset value to adjust deterministic latency. Range is 0..31*/
    0,              /* Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, '0' = not set*/
    0,              /* Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set*/
    0,              /* Flag for determining if CMOS mode for TX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS*/
    0               /* Flag for determining if API will calculate the appropriate settings for deframer lane in to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in deserializerLaneCrossbar will be used*/
};

static mykonosRxGainControl_t rxGainControl =
{
    MGC,            /* Current Rx gain control mode setting*/
    255,            /* Rx1 Gain Index, can be used in different ways for manual and AGC gain control*/
    255,            /* Rx2 Gain Index, can be used in different ways for manual and AGC gain control*/
    255,            /* Max gain index for the currently loaded Rx1 Gain table*/
    195,            /* Min gain index for the currently loaded Rx1 Gain table*/
    255,            /* Max gain index for the currently loaded Rx2 Gain table*/
    195,            /* Min gain index for the currently loaded Rx2 Gain table*/
    0,              /* Stores Rx1 RSSI value read back from the Mykonos*/
    0               /* Stores Rx2 RSSI value read back from the Mykonos*/
};

static mykonosORxGainControl_t orxGainControl =
{
    MGC,            /* Current ORx gain control mode setting*/
    255,            /* ORx1 Gain Index, can be used in different ways for manual and AGC gain control*/
    255,            /* ORx2 Gain Index, can be used in different ways for manual and AGC gain control*/
    255,            /* Max gain index for the currently loaded ORx Gain table*/
    237             /* Min gain index for the currently loaded ORx Gain table*/
};

static mykonosSnifferGainControl_t snifferGainControl =
{
    MGC,            /* Current Sniffer gain control mode setting*/
    255,            /* Current Sniffer gain index. Can be used differently for MANUAL Gain control/AGC*/
    255,            /* Max gain index for the currently loaded Sniffer Gain table*/
    203             /* Min gain index for the currently loaded Sniffer Gain table*/
};

static mykonosPeakDetAgcCfg_t rxPeakAgc =
{
    0x26,	/* apdHighThresh: */
    0x16,	/* apdLowThresh */
    0xB5,	/* hb2HighThresh */
    0x72,	/* hb2LowThresh */
    0x40,	/* hb2VeryLowThresh */
    0x06,	/* apdHighThreshExceededCnt */
    0x04,	/* apdLowThreshExceededCnt */
    0x06,	/* hb2HighThreshExceededCnt */
    0x04,	/* hb2LowThreshExceededCnt */
    0x04,	/* hb2VeryLowThreshExceededCnt */
    0x4,	/* apdHighGainStepAttack */
    0x2,	/* apdLowGainStepRecovery */
    0x4,	/* hb2HighGainStepAttack */
    0x2,	/* hb2LowGainStepRecovery */
    0x4,	/* hb2VeryLowGainStepRecovery */
    0x1,	/* apdFastAttack */
    0x1,	/* hb2FastAttack */
    0x1,	/* hb2OverloadDetectEnable */
    0x1,	/* hb2OverloadDurationCnt */
    0x1	/* hb2OverloadThreshCnt */
};

static mykonosPowerMeasAgcCfg_t rxPwrAgc =
{
    0x01,	/* pmdUpperHighThresh */
    0x03,	/* pmdUpperLowThresh */
    0x0C,	/* pmdLowerHighThresh */
    0x04,	/* pmdLowerLowThresh */
    0x4,	/* pmdUpperHighGainStepAttack */
    0x2,	/* pmdUpperLowGainStepAttack */
    0x2,	/* pmdLowerHighGainStepRecovery */
    0x4,	/* pmdLowerLowGainStepRecovery */
    0x08,	/* pmdMeasDuration */
    0x02	/* pmdMeasConfig */
};

static mykonosAgcCfg_t rxAgcConfig =
{
    255,	/* agcRx1MaxGainIndex */
    195,	/* agcRx1MinGainIndex */
    255,	/* agcRx2MaxGainIndex */
    195,	/* agcRx2MinGainIndex: */
    255,	/* agcObsRxMaxGainIndex */
    203,	/* agcObsRxMinGainIndex */
    1,		/* agcObsRxSelect */
    1,		/* agcPeakThresholdMode */
    1,		/* agcLowThsPreventGainIncrease */
    30720,	/* agcGainUpdateCounter */
    3,	/* agcSlowLoopSettlingDelay */
    4,	/* agcPeakWaitTime */
    0,	/* agcResetOnRxEnable */
    0,	/* agcEnableSyncPulseForGainCounter */
    &rxPeakAgc,
    &rxPwrAgc
};

static mykonosPeakDetAgcCfg_t obsRxPeakAgc =
{
    0x2A,	/* apdHighThresh: */
    0x16,	/* apdLowThresh */
    0xB5,	/* hb2HighThresh */
    0x72,	/* hb2LowThresh */
    0x40,	/* hb2VeryLowThresh */
    0x03,	/* apdHighThreshExceededCnt */
    0x03,	/* apdLowThreshExceededCnt */
    0x03,	/* hb2HighThreshExceededCnt */
    0x03,	/* hb2LowThreshExceededCnt */
    0x03,	/* hb2VeryLowThreshExceededCnt */
    0x4,	/* apdHighGainStepAttack */
    0x2,	/* apdLowGainStepRecovery */
    0x4,	/* hb2HighGainStepAttack */
    0x2,	/* hb2LowGainStepRecovery */
    0x4,	/* hb2VeryLowGainStepRecovery */
    0x0,	/* apdFastAttack */
    0x0,	/* hb2FastAttack */
    0x1,	/* hb2OverloadDetectEnable */
    0x1,	/* hb2OverloadDurationCnt */
    0x1		/* hb2OverloadThreshCnt */
};

static mykonosPowerMeasAgcCfg_t obsRxPwrAgc =
{
    0x01,	/* pmdUpperHighThresh */
    0x03,	/* pmdUpperLowThresh */
    0x0C,	/* pmdLowerHighThresh */
    0x04,	/* pmdLowerLowThresh */
    0x0,	/* pmdUpperHighGainStepAttack */
    0x0,	/* pmdUpperLowGainStepAttack */
    0x0,	/* pmdLowerHighGainStepRecovery */
    0x0,	/* pmdLowerLowGainStepRecovery */
    0x08,	/* pmdMeasDuration */
    0x02	/* pmdMeasConfig */
};

static mykonosAgcCfg_t obsRxAgcConfig =
{
    255,	/* agcRx1MaxGainIndex */
    195,	/* agcRx1MinGainIndex */
    255,	/* agcRx2MaxGainIndex */
    195,	/* agcRx2MinGainIndex: */
    255,	/* agcObsRxMaxGainIndex */
    203,	/* agcObsRxMinGainIndex */
    1,		/* agcObsRxSelect */
    1,		/* agcPeakThresholdMode */
    1,		/* agcLowThsPreventGainIncrease */
    30720,	/* agcGainUpdateCounter */
    3,		/* agcSlowLoopSettlingDelay */
    4,		/* agcPeakWaitTime */
    0,		/* agcResetOnRxEnable */
    0,		/* agcEnableSyncPulseForGainCounter */
    &obsRxPeakAgc,
    &obsRxPwrAgc
};


static mykonosRxProfile_t rxProfile =
{/* Rx 100MHz, IQrate 153.6MSPS, Dec5 */
    1,              /* The divider used to generate the ADC clock*/
    &rxFir,         /* Pointer to Rx FIR filter structure*/
    2,              /* Rx FIR decimation (1,2,4)*/
    5,              /* Decimation of Dec5 or Dec4 filter (5,4)*/
    1,              /* If set, and DEC5 filter used, will use a higher rejection DEC5 FIR filter (1=Enabled, 0=Disabled)*/
    1,              /* RX Half band 1 decimation (1 or 2)*/
    153600,         /* Rx IQ data rate in kHz*/
    100000000,      /* The Rx RF passband bandwidth for the profile*/
    100000,         /* Rx BBF 3dB corner in kHz*/
    NULL            /* pointer to custom ADC profile*/
};

static mykonosRxProfile_t orxProfile =
{/* ORX 240MHz, IQrate 307.2MSPS, Dec5 */
    1,              /* The divider used to generate the ADC clock*/
    &obsrxFir,      /* Pointer to Rx FIR filter structure or NULL*/
    1,              /* Rx FIR decimation (1,2,4)*/
    5,              /* Decimation of Dec5 or Dec4 filter (5,4)*/
    0,              /* If set, and DEC5 filter used, will use a higher rejection DEC5 FIR filter (1=Enabled, 0=Disabled)*/
    1,              /* RX Half band 1 decimation (1 or 2)*/
    307200,         /* Rx IQ data rate in kHz*/
    240000000,      /* The Rx RF passband bandwidth for the profile*/
    100000,         /* Rx BBF 3dB corner in kHz*/
    NULL            /* pointer to custom ADC profile*/
};


static mykonosRxProfile_t snifferProfile =
{ /* SRx 20MHz, IQrate 38.4MSPS, Dec5 */
    1,              /* The divider used to generate the ADC clock*/
    &snifferRxFir,  /* Pointer to Rx FIR filter structure or NULL*/
    4,              /* Rx FIR decimation (1,2,4)*/
    5,              /* Decimation of Dec5 or Dec4 filter (5,4)*/
    0,              /* If set, and DEC5 filter used, will use a higher rejection DEC5 FIR filter (1=Enabled, 0=Disabled)*/
    2,              /* RX Half band 1 decimation (1 or 2)*/
    38400,          /* Rx IQ data rate in kHz*/
    20000000,       /* The Rx RF passband bandwidth for the profile*/
    120000,         /* Rx BBF 3dB corner in kHz*/
    NULL            /* pointer to custom ADC profile*/
};



static mykonosTxProfile_t txProfile =
{ /* Tx 100/250MHz, IQrate 307.2MSPS, Dec5 */
    DACDIV_2p5,     /* The divider used to generate the DAC clock*/
    &txFir,         /* Pointer to Tx FIR filter structure*/
    1,              /* The Tx digital FIR filter interpolation (1,2,4)*/
    2,              /* Tx Halfband1 filter interpolation (1,2)*/
    1,              /* Tx Halfband2 filter interpolation (1,2)*/
    1,              /* TxInputHbInterpolation (1,2)*/
    307200,         /* Tx IQ data rate in kHz*/
    100000000,      /* Primary Signal BW*/
    250000000,      /* The Tx RF passband bandwidth for the profile*/
    236846,         /* The DAC filter 3dB corner in kHz*/
    125000,         /* Tx BBF 3dB corner in kHz*/
    0               /* Enable DPD, only valid for AD9373*/
};

static mykonosDigClocks_t mykonosClocks =
{
    122880,         /* CLKPLL and device reference clock frequency in kHz*/
   6144000,        /* CLKPLL VCO frequency in kHz*/
    VCODIV_1,       /* CLKPLL VCO divider*/
    4               /* CLKPLL high speed clock divider*/
};

static mykonosRxSettings_t  rxSettings =
{
    &rxProfile,     /* Rx datapath profile, 3dB corner frequencies, and digital filter enables*/
    &rxFramer,      /* Rx JESD204b framer configuration structure*/
    &rxGainControl, /* Rx Gain control settings structure*/
    &rxAgcConfig,   /* Rx AGC control settings structure*/
    1,              /* The desired Rx Channels to enable during initialization*/
    0,              /* Internal LO = 0, external LO*2 = 1*/
    900000000U,     /* Rx PLL LO Frequency (internal or external LO)*/
    0               /* Flag to choose if complex baseband or real IF data are selected for Rx and ObsRx paths. Where, if > 0 = real IF data, '0' = zero IF (IQ) data*/
};

static mykonosDpdConfig_t dpdConfig =
{
    5,              /* 1/2^(damping + 8) fraction of power `forgotten' per sample (default: `1/8192' = 5, valid 0 to 15), 0 = infinite damping*/
    1,              /* number of weights to use for int8_cpx weights weights member of this structure (default = 1)*/
    2,              /* DPD model version: one of four different generalized polynomial models: 0 = same as R0 silicon, 1-3 are new and the best one depends on the PA (default: 2)*/
    1,              /* 1 = Update saved model whenever peak Tx digital RMS is within 1dB of historical peak Tx RMS*/
    20,             /* Determines how much weight the loaded prior model has on DPD modeling (Valid 0 - 32, default 20)*/
    0,              /* Default off = 0, 1=enables automatic outlier removal during DPD modeling */
    512,            /* Number of samples to capture (default: 512, valid 64-32768)*/
    4096,           /* threshold for sample in AM-AM plot outside of 1:1 line to be thrown out. (default: 50% = 8192/2, valid 8192 to 1)*/
    0,              /* 16th of an ORx sample (16=1sample), (default 0, valid -64 to 64)*/
    255,            /* Default 255 (-30dBFs=(20Log10(value/8192)), (valid range  1 to 8191)*/
    {{64,0},{0,0},{0,0}}/* DPD model error weighting (real/imag valid from -128 to 127)*/
};

static mykonosClgcConfig_t clgcConfig =
{
    -2000,          /* (value = 100 * dB (valid range -32768 to 32767) - total gain and attenuation from Mykonos Tx1 output to ORx1 input in (dB * 100)*/
    -2000,          /* (value = 100 * dB (valid range -32768 to 32767) - total gain and attenuation from Mykonos Tx2 output to ORx2 input in (dB * 100)*/
    0,              /* (valid range 0 - 40dB), no default, depends on PA, Protects PA by making sure Tx1Atten is not reduced below the limit*/
    0,              /* (valid range 0 - 40dB), no default, depends on PA, Protects PA by making sure Tx2Atten is not reduced below the limit*/
    75,             /* valid range 1-100, default 75*/
    75,             /* valid range 1-100, default 45*/
    0,              /* 0= allow CLGC to run, but Tx1Atten will not be updated. User can still read back power measurements.  1=CLGC runs, and Tx1Atten automatically updated*/
    0,              /* 0= allow CLGC to run, but Tx2Atten will not be updated. User can still read back power measurements.  1=CLGC runs, and Tx2Atten automatically updated*/
    0,              /* 16th of an ORx sample (16=1sample), (default 0, valid -64 to 64)*/
    255,            /* Default 255 (-30dBFs=(20Log10(value/8192)), (valid range  1 to 8191)*/
    600,            /* Threshold for Tx1 in order to stop tracking, value = 100 * dB, default 6db then value = 600*/
    600,            /* Threshold for Tx2 in order to stop tracking, value = 100 * dB, default 6db then value = 600*/
    0,              /* Threshold feature enable for Tx1, 0 = disable, 1 = enable, default = 0*/
    0               /* Threshold feature enable for Tx1, 0 = disable, 1 = enable, default = 0*/
};

static mykonosVswrConfig_t vswrConfig =
{
    0,              /* 16th of an ORx sample (16=1sample), (default 0, valid -64 to 64)*/
    255,            /* Default 255 (-30dBFs=(20Log10(value/8192)), (valid range  1 to 8191)*/
    0,              /* 3p3V GPIO pin to use to control VSWR switch for Tx1 (valid 0-11) (output from Mykonos)*/
    1,              /* 3p3V GPIO pin to use to control VSWR switch for Tx2 (valid 0-11) (output from Mykonos)*/
    0,              /* 3p3v GPIO pin polarity for forward path of Tx1, opposite used for reflection path (1 = high level, 0 = low level)*/
    0,              /* 3p3v GPIO pin polarity for forward path of Tx2, opposite used for reflection path (1 = high level, 0 = low level)*/
    50,             /* Delay for Tx1 after flipping the VSWR switch until measurement is made. In us resolution*/
    50              /* Delay for Tx2 after flipping the VSWR switch until measurement is made. In us resolution*/
};

static mykonosTxSettings_t txSettings =
{
    &txProfile,     /* Tx datapath profile, 3dB corner frequencies, and digital filter enables*/
    &deframer,      /* Mykonos JESD204b deframer config for the Tx data path*/
    TX1,            /* The desired Tx channels to enable during initialization*/
    0,              /* Internal LO=0, external LO*2 if =1*/
    900000000U,     /* Tx PLL LO frequency (internal or external LO)*/
    TXATTEN_0P05_DB,/* Initial and current Tx1 Attenuation*/
    10000,          /* Initial and current Tx1 Attenuation mdB*/
    10000,          /* Initial and current Tx2 Attenuation mdB*/
    NULL,           /* DPD,CLGC,VSWR settings. Only valid for AD9373 device, set pointer to NULL otherwise*/
    NULL,           /* CLGC Config Structure. Only valid for AD9373 device, set pointer to NULL otherwise*/
    NULL            /* VSWR Config Structure. Only valid for AD9373 device, set pointer to NULL otherwise*/
};


static mykonosObsRxSettings_t obsRxSettings =
{
    &orxProfile,    /* ORx datapath profile, 3dB corner frequencies, and digital filter enables*/
    &orxGainControl,/* ObsRx gain control settings structure*/
    &obsRxAgcConfig,/* ORx AGC control settings structure*/
    &snifferProfile,/* Sniffer datapath profile, 3dB corner frequencies, and digital filter enables*/
    &snifferGainControl,/* SnRx gain control settings structure*/
    &obsRxFramer,   /* ObsRx JESD204b framer configuration structure */
    (MYK_ORX1_ORX2 | MYK_SNRXA_B_C),/* obsRxChannel */
    OBSLO_TX_PLL,   /* (obsRxLoSource) The Obs Rx mixer can use the Tx Synth(TX_PLL) or Sniffer Synth (SNIFFER_PLL) */
    900000000U,     /* SnRx PLL LO frequency in Hz */
    0,              /* Flag to choose if complex baseband or real IF data are selected for Rx and ObsRx paths. Where if > 0 = real IF data, '0' = complex data*/
    NULL,           /* Custom Loopback ADC profile to set the bandwidth of the ADC response */
    OBS_RXOFF       /* Default ObsRx channel to enter when radioOn called */
};

static mykonosArmGpioConfig_t armGpio =
{
    0,	// useRx2EnablePin; /*!< 0= RX1_ENABLE controls RX1 and RX2, 1 = separate RX1_ENABLE/RX2_ENABLE pins */
    0,	// useTx2EnablePin; /*!< 0= TX1_ENABLE controls TX1 and TX2, 1 = separate TX1_ENABLE/TX2_ENABLE pins */
    0,	// txRxPinMode;     /*!< 0= ARM command mode, 1 = Pin mode to power up Tx/Rx chains */
    0,	// orxPinMode;      /*!< 0= ARM command mode, 1 = Pin mode to power up ObsRx receiver*/

    /*Mykonos ARM input GPIO pins -- Only valid if orxPinMode = 1 */
    0,	// orxTriggerPin; /*!< Select desired GPIO pin (valid 4-15) */
    0,	// orxMode2Pin;   /*!< Select desired GPIO pin (valid 0-18) */
    0,	// orxMode1Pin;   /*!< Select desired GPIO pin (valid 0-18) */
    0,	// orxMode0Pin;   /*!< Select desired GPIO pin (valid 0-18) */

    /* Mykonos ARM output GPIO pins  --  always available, even when pin mode not enabled*/
    0,	// rx1EnableAck;  /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
    0,	// rx2EnableAck;  /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
    0,	// tx1EnableAck;  /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
    0,	// tx2EnableAck;  /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
    0,	// orx1EnableAck;  /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
    0,	// orx2EnableAck;  /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
    0,	// srxEnableAck;  /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
    0 	// txObsSelect;   /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
    /* When 2Tx are used with only 1 ORx input, this GPIO tells the BBIC which Tx channel is   */
    /* active for calibrations, so BBIC can route correct RF Tx path into the single ORx input*/
};

static mykonosGpio3v3_t gpio3v3 =
{
    0,				/*!< Oe per pin, 1=output, 0 = input */
    GPIO3V3_BITBANG_MODE,	/*!< Mode for GPIO3V3[3:0] */
    GPIO3V3_BITBANG_MODE,	/*!< Mode for GPIO3V3[7:4] */
    GPIO3V3_BITBANG_MODE,	/*!< Mode for GPIO3V3[11:8] */
};

static mykonosGpioLowVoltage_t gpio =
{
    0,/* Oe per pin, 1=output, 0 = input */
    GPIO_MONITOR_MODE,/* Mode for GPIO[3:0] */
    GPIO_MONITOR_MODE,/* Mode for GPIO[7:4] */
    GPIO_MONITOR_MODE,/* Mode for GPIO[11:8] */
    GPIO_MONITOR_MODE,/* Mode for GPIO[15:12] */
    GPIO_MONITOR_MODE,/* Mode for GPIO[18:16] */
};

static mykonosAuxIo_t mykonosAuxIo =
{
    0,	//auxDacEnableMask uint16_t
    {0,0,0,0,0,0,0,0,0,0},	 //AuxDacValue uint16[10]
    {0,0,0,0,0,0,0,0,0,0},	 //AuxDacSlope uint8[10]
    {0,0,0,0,0,0,0,0,0,0},	 //AuxDacVref uint8[10]
    &gpio3v3,	//pointer to gpio3v3 struct
    &gpio,	//pointer to gpio1v8 struct
    &armGpio
};

static spiSettings_t mykSpiSettings =
{
    2, /* chip select index - valid 1~8 */
    0, /* the level of the write bit of a SPI write instruction word, value is inverted for SPI read operation */
    1, /* 1 = 16-bit instruction word, 0 = 8-bit instruction word */
    1, /* 1 = MSBFirst, 0 = LSBFirst */
    0, /* clock phase, sets which clock edge the data updates (valid 0 or 1) */
    0, /* clock polarity 0 = clock starts low, 1 = clock starts high */
    0, /* Not implemented in ADIs platform layer. SW feature to improve SPI throughput */
    1, /* Not implemented in ADIs platform layer. For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr=addr-1 */
    1  /* 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode */
};

static mykonosTempSensorConfig_t tempSensor =
{
    7,              /* 3-bit value that controls the AuxADC decimation factor when used for temp sensor calculations; AuxADC_decimation = 256 * 2^tempDecimation*/
    67,             /* 8-bit offset that gets added to temp sensor code internally*/
    1,              /* this bit overrides the factory-calibrated fuse offset and uses the value stored in the offset member*/
    15,             /* 4-bit code with a resolution of 1°C/LSB, each time a temperature measurement is performed, the device compares the current temperature against the previous value.*/
};

static mykonosTempSensorStatus_t tempStatus =
{
    0,              /* 16-bit signed temperature value (in deg C) that is read back*/
    0,              /* If the absolute value of the difference is greater than the value in temperature configuration tempWindow, the windowExceeded flag is set.*/
    0,              /* when windowExceeded member gets set, this bit is set to 1 if current value is greater than previous value, else reset*/
    0,              /* when the reading is complete and a valid temperature value stored in tempCode.*/
};

mykonosDevice_t mykDevice =
{
    &mykSpiSettings,    /* SPI settings data structure pointer */
    &rxSettings,        /* Rx settings data structure pointer */
    &txSettings,        /* Tx settings data structure pointer */
    &obsRxSettings,     /* ObsRx settings data structure pointer */
    &mykonosAuxIo,          /* Auxiliary IO settings data structure pointer */
    &mykonosClocks,     /* Holds settings for CLKPLL and reference clock */
    0                   /* Mykonos initialize function uses this as an output to remember which profile data structure pointers are valid */
};

myk_ad9528init.c

/* AD9528 data structure initialization file */

/**
* \page Disclaimer Legal Disclaimer
* Copyright 2015-2017 Analog Devices Inc.
* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file.
*
*/


#include <stdint.h>
#include "common.h"
#include "t_ad9528.h"

static spiSettings_t clockSpiSettings =
{
     1,         /* chip select Index */
     0,         /* Write bit polarity */
     1,         /* 16bit instruction word */
     1,         /* MSB first */
     0,         /* Clock phase */
     0,         /* Clock polarity */
     0,         /* uint8_t enSpiStreaming */
     1,         /* uint8_t autoIncAddrUp */
     1,         /* uint8_t fourWireMode */
     25000000   /* spiClkFreq_Hz */   
};

ad9528pll1Settings_t clockPll1Settings =
{
    30720000,
    1,
    3,
    0,
    1,
    0,
    122880000,
    2,
    4
};

ad9528pll2Settings_t clockPll2Settings =
{
    3,
    10,
    30
};

ad9528outputSettings_t clockOutputSettings =
{
    53237,
    {0,0,0,2,0,0,0,0,0,0,0,0,2,0},
    {0,0,0,2,0,0,0,0,0,0,0,0,0,0},
    {0,0,0,2,0,0,0,0,0,0,0,0,0,0},
    {0,0,0,2,0,0,0,0,0,0,0,0,0,0},
    {10,10,10,10,10,10,10,10,10,10,10,10,10,10},
    {122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000}
};

ad9528sysrefSettings_t clockSysrefSettings =
{
   0,
   2,
   0,
   0,
   0,
   0,
   512
};

ad9528Device_t clockAD9528_ =
{
    &clockSpiSettings,
    &clockPll1Settings,
    &clockPll2Settings,
    &clockOutputSettings,
    &clockSysrefSettings
};

Porting zc706-adrv9371 HDL to custom xc7z035: JESD204 TX fails with CPLL/QPLL unlocked

Danial25548 — Thu, 05 Feb 2026 17:46:03 GMT

Hello everyone

I am trying to port the official HDL reference design for zc706-adrv9371 to my custom Zynq-7000 board (xc7z035) using ADRV9371-W/PCBZ (FMC).

1) Hardware setup

Custom carrier: Zynq 7000 xc7z035
RF card: ADRV9371-W/PCBZ
Connection: HPC FMC (REFCLK + SYSREF + JESD lanes)
AD9528 on the ADRV9371 provides FMC clocks:
- out_altvoltage1_FMC_CLK_frequency
- out_altvoltage3_FMC_SYSREF_frequency
- out_altvoltage13_DEV_CLK_frequency
- out_altvoltage12_DEV_SYSREF_frequency

2) What I did (HDL + Linux)

Took the zc706-adrv9371 HDL design from ADI HDL repo.
Ported it for my board:
- Updated TCL (project/board setup)
- Updated XDC (pinout for FMC signals / ref_clk pins / constraints)
- Updated system_top.v (top-level ports mapping to my board)

ez.analog.com/.../2555.System_5F00_top.txt

Generated the bitstream + XSA
Built PetaLinux:
- Used device-tree approach similar to zc706 project
- Generated BOOT files (BOOT.BIN, image.ub, etc.)
Linux boots fine and the drivers probe:
- axi-jesd204-rx, axi-jesd204-tx
- axi-adxcvr-{tx,rx,rx-os}
- ad9371-phy appears in IIO

3) Current problem

ez.analog.com/.../4812.Linux_5F00_logs.txt

The JESD link never comes up. I get errors like:

axi_adxcvr_drv 44a80000.axi-adxcvr-tx: CPLL TX Unlocked Error: 10
(sometimes it shows QPLL depending on build/config)
axi-jesd204-tx ... Link0 enable lane clock failed (-5)
JESD FSM rolls back during clk_sync_stage3 / link_setup

Also:

Measured Link Clock: off
Link is disabled
RX lanes stay CGS state: INIT and Initial Frame Synchronization: No

4) Debugging steps already tried

A) Verified AD9528 IIO nodes exist

I can read the AD9528 output frequencies from sysfs, for example:

out_altvoltage1_FMC_CLK_frequency = 122880000 (default)
out_altvoltage13_DEV_CLK_frequency = 122880000
SYSREF nodes exist and show 60000 (60 kHz)

B) Tested changing FMC_CLK frequency

I tried to write other clock rates into:

/sys/bus/iio/devices/iio:deviceX/out_altvoltage1_FMC_CLK_frequency
and then echo 1 > sync_dividers.

Some values are accepted (e.g., 153.6 MHz, 245.76 MHz, 307.2 MHz), but the JESD TX still fails with the same CPLL/QPLL TX Unlocked Error and enable lane clock failed.

C) Checked Linux clock framework

/sys/kernel/debug/clk/clk_summary shows ad9528-1_out1 and also clocks like tx_out_clk, tx_gt_clk, etc., but when the failure happens, the lane clock is never established and JESD stays disabled.

D) Tried reset sequencing / re-enabling drivers

Forced ensm_mode=radio_off
Disabled/enabled JESD cores (echo 0/1 > .../enable)
Disabled/enabled transceiver cores (axi-adxcvr)
Unbind/bind platform drivers

The failure persists.

E) Vivado timing / clock period constraints

I also adjusted create_clock constraints for ref clocks (example: 8.0 ns vs 8.138 ns) but this does not fix the issue. The failure appears hardware/clocking related (PLL not locking).

5) My understanding / question

My understanding is:

AD9528 FMC_CLK → goes through FMC → arrives to FPGA pins ref_clk*_p/n → becomes GTREFCLK → used by Xilinx GTX QPLL→ creates TX serial clock → provides lane_clk for AXI-JESD204-TX.

So the message axi_adxcvr... CPLL/QPLL TX Unlocked is coming from the FPGA transceiver PLL not locking.

Question:
What are the most likely causes for GTX QPLL not locking in this porting case?

Specifically, I would like guidance on what to verify first:

Refclk frequency mismatch vs the GTX configuration / JESD lane rate
Wrong refclk pin mapping / IBUFDS_GTE2 usage / polarity issues
Any required constraints or resets for GTX reference clocks
Any known requirements in the zc706 design (Si5324/clocking assumptions) that do not apply directly to ADRV9371 FMC clocking

TES feature request: transceiver output sample magnitude view

RKH — Fri, 30 Jan 2026 00:18:12 GMT

Would it be possible to provide the feature within TES to view the transceiver output sample magnitudes [sqrt(I^2+Q^2)] with either linear or log scaling?

Thanks

ZCU102+AD9371

PavankumarV — Fri, 30 Jan 2026 00:15:46 GMT

hi all, i have ZCU102+AD9371, i am new to Programming and want to learn and implement frequency measurement algorithm. share if any links or docs for quick start.

thanks in advance.

ad9371 +40MHz offset in Tx

RFSOM — Fri, 30 Jan 2026 00:14:43 GMT

hello, with default configuration, I see +40Mhz offset in the Tx of AD9371. moving the LO moves the offset so 2500MHz transmit at 2540. disabling Tx channles, destroying buffer and falsing the cyclic transmit DO NOT stop the transmit. only builidng a new waveform and transmitting it aligns the transmit freq. Once destoying the buffer, the signal jumps again to the +40MHz offset to the respective LO. the signal is strong

AD9371 Mykonos Charge Pump Error

RMahar — Fri, 30 Jan 2026 00:14:28 GMT

I am developing a setup using a custom AD9371 board with the ZC706 for the baseband processor. On some units, I intermittently get the following debug message during configuration:

clock locked
BBIC JESD204B Initialization
Mykonos Initialization
MESSAGE: 0: MYKONOS_resetDevice()

MESSAGE: 0: MYKONOS_initialize()

MESSAGE: 0: MYKONOS_verifyDeviceDataStructure()

MESSAGE: 0: MYKONOS_verifyProfiles()

MESSAGE: 0: MYKONOS_setSpiSettings()

MESSAGE: 0: MYKONOS_initDigitalClocks()

MESSAGE: 0: MYKONOS_calculateScaledDeviceClk_kHz()

MESSAGE: 0: MYKONOS_waitForEvent()

WARNING: 233: Clock PLL Charge Pump Cal event timed out in MYKONOS_waitForEvent()

Clock PLL Charge Pump Cal event timed out in MYKONOS_waitForEvent()

MESSAGE: 0: MYKONOS_checkPllsLockStatus()

PLL not locked

As this does not happen on all boards or consistently on all power ups, what should I look at for troubleshooting?

ZCU102 and ADRV9371

Maxplus — Fri, 30 Jan 2026 00:14:20 GMT

I have a ZCU102 rev1 board, and ADRV9371 eval board that I'm starting a project on.

I manage to communicate with the ADI IIO Scope Capture.

However, I like to use the ADRV9371 TESS but the software is not seeing it. Not sure why this is happening as it is ok with ADI IIO.

Is it possible to operate the TESS with ZCU102 and ADRV9371?

Regarding the scope capture, I can see plots in the time domain. Are these individual I and Q components or is it the magnitude of sqrt (I^2 + Q^2)? Thank you

Maximum and Minimum Sampling Rates for Tx and Rx in AD9371 with TES or FilterWizard application

IttyGayathri — Fri, 30 Jan 2026 00:13:21 GMT

I am currently working with the AD9371 RF transceiver and using either the Transceiver Evaluation Software (TES) or the AD9371 FilterWizard application for a No-OS application. I need to configure the sampling rates for both the Tx and Rx paths.

Could someone provide me with the maximum and minimum sampling rates that can be configured for Tx and Rx using these tools or is there any other tools where I can configure the minimum sampling rate less than 50MHz and above 500MHz?

Specifically:

What is the maximum and minimum sampling rate that can be set for Tx (transmit) in TES or FilterWizard?
What is the maximum and minimum sampling rate that can be set for Rx (receive) in TES or FilterWizard?

If there are any additional considerations or constraints when setting these rates, such as specific configurations or limitations based on the sampling rate, I would appreciate that information as well.

Thank you in advance for your help!

Configuring AD9371 for Integer IQ Sample Rate Below 49.152 MHz in No OS Application:

IttyGayathri — Fri, 30 Jan 2026 00:12:49 GMT

I am working on an AD9371 and ZC706 No OS application, configuring the AD9371 transceiver with a fixed device clock of 122.88 MHz. To ensure compatibility with my system, I need to achieve an IQ sample rate that is an integer and less than 49.152 MHz. Is there any TES gui software source, for changing the device clock.

I have attempted to configure the transceiver using the available settings but have not yet achieved the desired integer sample rate below 49.152 MHz. Could anyone confirm if my approach is correct, or if there are any other methods or configurations I should consider to achieve this?

Any insights or suggestions would be greatly appreciated. Thank you!

PLL LOCK STATUS for AD9371

Prasanth89 — Fri, 30 Jan 2026 00:12:45 GMT

Good Morning Sir / Madam,

we are working on AD9371 evaluation board with xilinx linux drivers.

Our application needs to set continuously RX RF LO at a speed off 500microsecond.

so would like to know the following

a) what is the PLL settling time

b) how to check PLL lock status from user code.

c) How to reduce the settling time if required.

How to Dynamic Configuration of Sampling Frequencies, Device Frequency, and Bandwidth for AD9371 and AD9358 Without Using Mykonos.c Files from TEST Software

IttyGayathri — Fri, 30 Jan 2026 00:12:08 GMT

I'm working with the AD9371 and AD9358 RF transceivers on a ZC706 evaluation board. My project involves configuring the sampling frequencies, device frequency, and bandwidth for these transceivers. So far, I've been using the TES (Transceiver Evaluation Software) to generate the necessary Mykonos.c files, which I then integrate into my project.

However, I would like to streamline this process by dynamically configuring these parameters directly from my code instead of relying on pre-generated Mykonos.c files.

Could anyone provide guidance on how to achieve this? Are there specific API functions or register settings that can be used for dynamic configuration? Any sample code or references to relevant documentation would be greatly appreciated.

Thank you in advance for your help!

Configuring AD9371 for Integer IQ Sample Rate Below 49.152 MHz in No OS Application:

Xdlinx — Fri, 30 Jan 2026 00:11:56 GMT

Any insights or suggestions would be greatly appreciated. Thank you!

Disabling ORX channel and allocating all four JESD lanes to RX

gavint — Fri, 30 Jan 2026 00:11:47 GMT

Hello

I have an ADRV9375 evaluation board that I am using with a ZCU102. I have used the ADI 2022_R2 HDL reference design to build the FPGA firmware in Vivado. I am using the ADI 2022_R2 meta ADI layer in Petalinux. It is working in the following configuration:

RX: 125MSPS, 2 channels, 2 JESD lanes

ORX: 250MSPS, 1 channel, 2 JESD lanes

TX: 250MSPS, 2 channels, 4 JESD lanes

The customer has now requested that I change the configuration and allocate all four RX JESD lanes to the RX channel. So the configuration becomes:

RX: 166.67MSPS, 2 channels, 4 JESD lanes

ORX: 166.67MSPS, only internal to the AD9375, no data to the FPGA

TX: 166.67MSPS, 2 channels, 4 JESD lanes

I am about to start making the changes to the FPGA HDL firmware so that all four RX JESD lanes are allocated to the RX.

However, I wanted to check:

1) Is this configuration (all 4 lanes allocated to RX with no OBS RX) supported by the IIO Linux device driver?

2) If so, what are the required updates to the device tree to support this configuration? I assume I need to make changes to the JESD framer configuration in the device tree.

3) If not, how extensive would the changes need to be to the IIO Linux device driver to support this mode? Some guidance would be greatly appreciated.

Thank you.

Issue with the SPI for ADRV9371 Board on a VCU108

L.Christin — Fri, 30 Jan 2026 00:11:24 GMT

Hello,

We are working with the ADRV9371, but we get an issue when we try to communicate by the SPI. We use the Xilinx SPI IP on a VCU108, with a Micro blaze MCU to implement the Mykonos code.

We put both Resetb and FMC_clk_resetb to one, and we have something coming out from the FPGA SPI, we checked it with a probe and everything is going through the FMC connector as it should be.

But at the moment we can’t get any response coming back from the Analog device board, but it’s working with the TES software on a ZC706. We compared the frame shape and they match (clock polarity and phases are good).

Did we forgot something that is essential for the AD9371 evaluation board?
Also what is the purpose of the HAL_initSpi() in CMB_setSPIOptions() because we don´t have any information about this, what do we need to do to replace it? It is used to change the register of the AD9371 SPI or only for the FPGA?
In the constraint file we can´t use the IOSTANDARD LVCMOS25 we can only use LVCMOS18, can we have issue due to that with the High level?

Best regards.

How Do I load the Binary File into an AD9373?

DaveTacoma — Fri, 30 Jan 2026 00:10:55 GMT

1. It seems that we need to load a binary file into the AD9371 ARM processor as part of the boot-up procedure. Is “Mykonos_M3.bin” the name of the correct binary file, or is there a more recent version?

2. Does the binary file get loaded into the ARM processor using the SPI interface, or is there some other method which is used? Can I get a copy of the source code for the ARM init procedure?

3. Is the SPI interface implemented as an HDL object, or is it implemented by “bit banging”? Did you use code for this which was supplied by Analog Devices, or did you write it yourself? Can I get a copy of the SPI drivers and/or SPI IP core?

4. Is the SPI driver used for the initialization of the ARM the same driver used for sending Tx and Rx commands to the chip?

TES GUI Source Code

myZone2180 — Fri, 30 Jan 2026 00:10:41 GMT

Is the latest release of the Windows TES GUI 2.0.68 Source Code available? Or earlier releases?

Looking for example IronPython or C code for reading(writing) I/Q data from(to) AD9371 Zynq platform in a Windows aplication.

AD9375 CFR

Yashar — Fri, 30 Jan 2026 00:10:25 GMT

May I ask you to know whether i can control the CFR of signal with AD9375'S SOFTWARE?! OR we can not control it at all?

Algorithm negotiation fail

Ivan18 — Fri, 30 Jan 2026 00:08:26 GMT

Hi,

I'm using the AD9371 Transceiver Evaluation Software but when I try to connect I have the next error message: Algorithm negotiation fail; Platform problem: Algorithm negotiation fail. On the right botoom corner I have the nextone message: Please update SD card, but I have the last version of OS.

Now, I have a setup with both boards on a AP and my host PC too using DHCP for IP configuration. When I do "ping" between my PC and the boad I get a connection and the other way around as well. I have unzipped the src folder (Wideband RF Transceiver Evaluation Software | Analog Devices) in the directory "/" on my board, I dont have run nothing of this new directory because I dont have read about it.

Regards.

SPI API control of TX datapath attenuation -- Value discrepancy

Matt_Centauri — Fri, 30 Jan 2026 00:08:20 GMT

Tx attenuation step size is set to 0.05 dB (TXATTEN_0P05_DB)

When running the following API -- MYKONOS_setTx1Attenuation(&device,15000) -- I am trying to attenuate by 15 decibels. This is within range of the TX attenuation, from 0 - 41.95 dB.

However, later on when I call the get API -- MYKONOS_getTx1Attenuation(&device,&atten) -- the attenuation value shown is 17000 mdB. Nowhere else do I set the attenuation to this value via the API calls.

Any idea why this discrepancy is happening? The step size should not be an issue, but even if it were the value should be lower, not higher.

Experiencing inconsistency with MYKONOS_waitInitCal timing out With the TX_QEC init cal flag enabled

Matt_Centauri — Fri, 30 Jan 2026 00:08:16 GMT

We're running into an issue where 9.7% of the time MYKONOS_waitInitCals returns the error: MYKONOS_ERR_WAIT_INITCALS_ARMERROR. The data we measured was over a span of 1300+ configurations of the chip across a few unique mykonos profiles. This specific error is split evenly across profiles that target RX and TX only configurations. To be clear, the profilesValid mask is set to 0x7, which means the TX,RX, and ORX profiles are valid, however when we run a "TX only" configuration we only run initial calibrations for the TX side (including the QEC calibration). Same goes for RX only configuration.

Essentially, 5% of the time our configuration sequence times out for initial calibrations when we used TX calibration flags, and 5% of the time it happens with RX.

The kicker to all of this is, 90% of the time we don't experience these timeouts on the same set of unique configurations. As I mentioned, we logged this data over 1300+ configuration sequences, but there's a small set of unique configurations that are getting repeated. So the question is, why does the MYKONOS_waitInitCals timeout so inconsistently? Why does this number drop to zero when QEC calibration flags are commented out?

I tried looking at similar posts to this forum about this very issue but it doesn't seem to be very clear. One thing mentioned is making sure the ports are impedance matched, but these configurations are all happening in the same environment so why would it fail 10% of the time?