Hello ,
I am working on a custom AD9371 + ZU15EG design and am seeing the "SYSREF Alignment Error = Yes" status intermittently after some power cycles. Most power-ons work correctly, but occasionally the alignment error is reported.
Iam using reference project HDL and NO OS project provided in ADI github.
I reviewed the ADI JESD troubleshooting documentation and found two possible causes:
SYSREF frequency is not an integer multiple/submultiple of the LMFC frequency
SYSREF violating setup/hold timing with respect to the JESD device clock
For our configuration:
Lane rate = 2457.6 Mbps
F = 2 octets/frame
K = 32 frames/multiframe
LMFC frequency = 3.84 MHz
SYSREF frequency = 0.96 MHz
Since SYSREF = LMFC/4, the first condition appears to be satisfied.
Regarding the second point, the troubleshooting guide suggests constraining the SYSREF path relative to the device clock. We would like to investigate this further.
Our clocking setup is as follows:
HMC7044 generates both clocks and SYSREF.
Clock and SYSREF traces are length matched on the PCB.
AD9371 reference clock = 122.88 MHz.
We are using the standard 61.44 MHz profile configuration files from the ADI reference design.
In the HDL reference design, the JESD device clock is generated by a Clock Wizard whose input is the GT Channel 0 output clock, and the Clock Wizard output is used as the device clock for the JESD IP.
My questions are:
In this architecture, what clock should be used as the timing reference when constraining the SYSREF path?
How should the SYSREF path be constrained in Vivado?
Has anyone observed intermittent SYSREF alignment errors in a similar AD9371 setup despite having matched clock/SYSREF routing?
Besides SYSREF frequency relationship and setup/hold timing, are there any other common causes that could lead to intermittent SYSREF alignment errors across power cycles?
Any guidance or recommendations would be greatly appreciated. Thanks.
