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The AD9528 is a two-stage PLL with an integrated JESD204B/JESD204C SYSREF generator for multiple device synchronization. The first stage phase-locked loop...
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Porting zc706-adrv9371 HDL to custom xc7z035: JESD204 TX fails with CPLL/QPLL unlocked

		
	
				

			

									
					    Danial25548
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Feb 5, 2026 
				
			
			
		
    
		
		                    	    
    
        	    
    Thread Summary
    
                The user is experiencing issues with the GTX QPLL not locking and JESD204 link failing on a custom Zynq-7000 (xc7z035) board with ADRV9371-W/PCBZ. The final answer indicates that the AD9371 cannot support a 7.68 MSPS sample rate, with the minimum supported rate being 30 MSPS. The user should consider up-sampling in the FPGA to meet the required LTE baseband rates.
                        	    
    
                
                     AI Generated Content
                
    	    
    
             
				
        		
    
		    
		    		    
    
		      		            		        
    Category: Software
    
    		        		            		    
    Product Number:  adrv9371 
    
    		        		    		    
    
		    		    
		    			
    
			    
    Hello everyone
    

    I am trying to port the official HDL reference design for zc706-adrv9371 to my custom Zynq-7000 board (xc7z035) using ADRV9371-W/PCBZ (FMC).
    

    1) Hardware setup
    

      

    • 

      Custom carrier: Zynq 7000 xc7z035
      

      • 

    • 

      RF card: ADRV9371-W/PCBZ
      

      • 

    • 

      Connection: HPC FMC (REFCLK + SYSREF + JESD lanes)
      

      • 

    • 

      AD9528 on the ADRV9371 provides FMC clocks:
      

        

      • 

        out_altvoltage1_FMC_CLK_frequency
        

        • 

      • 

        out_altvoltage3_FMC_SYSREF_frequency
        

        • 

      • 

        out_altvoltage13_DEV_CLK_frequency
        

        • 

      • 

        out_altvoltage12_DEV_SYSREF_frequency
        

        • 

      

      • 

    

    2) What I did (HDL + Linux)
    

      

    1. 

      Took the zc706-adrv9371 HDL design from ADI HDL repo.
      

      2. 

    2. 

      Ported it for my board:
      

        

      • 

        Updated TCL (project/board setup)
        

        • 

      • 

        Updated XDC (pinout for FMC signals / ref_clk pins / constraints)
        

        • 

      • 

        Updated system_top.v (top-level ports mapping to my board)
        

        • 

      

      3. 

    

    



    
    
    
        Fullscreen
        2555.System_top.txt
        Download
    
    
    
    // ***************************************************************************
// ***************************************************************************
// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
//   1. The GNU General Public License version 2 as published by the
//      Free Software Foundation, which can be found in the top level directory
//      of this repository (LICENSE_GPL2), and also online at:
//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
//   2. An ADI specific BSD license, which can be found in the top level directory
//      of this repository (LICENSE_ADIBSD), and also on-line at:
//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
//      This will allow to generate bit files and not release the source code,
//      as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************

`timescale 1ns/100ps

module system_top (

  inout       [14:0]      ddr_addr,
  inout       [ 2:0]      ddr_ba,
  inout                   ddr_cas_n,
  inout                   ddr_ck_n,
  inout                   ddr_ck_p,
  inout                   ddr_cke,
  inout                   ddr_cs_n,
  inout       [ 3:0]      ddr_dm,
  inout       [31:0]      ddr_dq,
  inout       [ 3:0]      ddr_dqs_n,
  inout       [ 3:0]      ddr_dqs_p,
  inout                   ddr_odt,
  inout                   ddr_ras_n,
  inout                   ddr_reset_n,
  inout                   ddr_we_n,

  inout                   fixed_io_ddr_vrn,
  inout                   fixed_io_ddr_vrp,
  inout       [53:0]      fixed_io_mio,
  inout                   fixed_io_ps_clk,
  inout                   fixed_io_ps_porb,
  inout                   fixed_io_ps_srstb,

  inout       [14:0]      gpio_bd,


  inout                   iic_scl,
  inout                   iic_sda,

  input                   ref_clk0_p,
  input                   ref_clk0_n,
  input                   ref_clk1_p,
  input                   ref_clk1_n,
  input       [ 3:0]      rx_data_p,
  input       [ 3:0]      rx_data_n,
  output      [ 3:0]      tx_data_p,
  output      [ 3:0]      tx_data_n,
  output                  rx_sync_p,
  output                  rx_sync_n,
  output                  rx_os_sync_p,
  output                  rx_os_sync_n,
  input                   tx_sync_p,
  input                   tx_sync_n,
  input                   sysref_p,
  input                   sysref_n,

  output                  spi_csn_ad9528,
  output                  spi_csn_ad9371,
  output                  spi_clk,
  output                  spi_mosi,
  input                   spi_miso,

  inout                   ad9528_reset_b,
  inout                   ad9528_sysref_req,
  inout                   ad9371_tx1_enable,
  inout                   ad9371_tx2_enable,
  inout                   ad9371_rx1_enable,
  inout                   ad9371_rx2_enable,
  inout                   ad9371_test,
  inout                   ad9371_reset_b,
  inout                   ad9371_gpint,

  inout                   ad9371_gpio_00,
  inout                   ad9371_gpio_01,
  inout                   ad9371_gpio_02,
  inout                   ad9371_gpio_03,
  inout                   ad9371_gpio_04,
  inout                   ad9371_gpio_05,
  inout                   ad9371_gpio_06,
  inout                   ad9371_gpio_07,
  inout                   ad9371_gpio_15,
  inout                   ad9371_gpio_08,
  inout                   ad9371_gpio_09,
  inout                   ad9371_gpio_10,
  inout                   ad9371_gpio_11,
  inout                   ad9371_gpio_12,
  inout                   ad9371_gpio_14,
  inout                   ad9371_gpio_13,
  inout                   ad9371_gpio_17,
  inout                   ad9371_gpio_16,
  inout                   ad9371_gpio_18


);

  // internal signals

  wire    [63:0]  gpio_i;
  wire    [63:0]  gpio_o;
  wire    [63:0]  gpio_t;
  wire            ref_clk0;
  wire            ref_clk1;
  wire            rx_sync;
  wire            rx_os_sync;
  wire            tx_sync;
  wire            sysref;

  // instantiations

  IBUFDS_GTE2 i_ibufds_rx_ref_clk (
    .CEB (1'd0),
    .I (ref_clk0_p),
    .IB (ref_clk0_n),
    .O (ref_clk0),
    .ODIV2 ());

  IBUFDS_GTE2 i_ibufds_ref_clk1 (
    .CEB (1'd0),
    .I (ref_clk1_p),
    .IB (ref_clk1_n),
    .O (ref_clk1),
    .ODIV2 ());

  BUFG i_bufg_ref_clk (
    .I (ref_clk1),
    .O (ref_clk1_bufg));

  OBUFDS i_obufds_rx_sync (
    .I (rx_sync),
    .O (rx_sync_p),
    .OB (rx_sync_n));

  OBUFDS i_obufds_rx_os_sync (
    .I (rx_os_sync),
    .O (rx_os_sync_p),
    .OB (rx_os_sync_n));

  IBUFDS i_ibufds_tx_sync (
    .I (tx_sync_p),
    .IB (tx_sync_n),
    .O (tx_sync));

  IBUFDS i_ibufds_sysref (
    .I (sysref_p),
    .IB (sysref_n),
    .O (sysref));

  ad_iobuf #(
    .DATA_WIDTH(28)
  ) i_iobuf (
    .dio_t ({gpio_t[59:32]}),
    .dio_i ({gpio_o[59:32]}),
    .dio_o ({gpio_i[59:32]}),
    .dio_p ({ ad9528_reset_b,       // 59
              ad9528_sysref_req,    // 58
              ad9371_tx1_enable,    // 57
              ad9371_tx2_enable,    // 56
              ad9371_rx1_enable,    // 55
              ad9371_rx2_enable,    // 54
              ad9371_test,          // 53
              ad9371_reset_b,       // 52
              ad9371_gpint,         // 51
              ad9371_gpio_00,       // 50
              ad9371_gpio_01,       // 49
              ad9371_gpio_02,       // 48
              ad9371_gpio_03,       // 47
              ad9371_gpio_04,       // 46
              ad9371_gpio_05,       // 45
              ad9371_gpio_06,       // 44
              ad9371_gpio_07,       // 43
              ad9371_gpio_15,       // 42
              ad9371_gpio_08,       // 41
              ad9371_gpio_09,       // 40
              ad9371_gpio_10,       // 39
              ad9371_gpio_11,       // 38
              ad9371_gpio_12,       // 37
              ad9371_gpio_14,       // 36
              ad9371_gpio_13,       // 35
              ad9371_gpio_17,       // 34
              ad9371_gpio_16,       // 33
              ad9371_gpio_18}));    // 32

  ad_iobuf #(
    .DATA_WIDTH(15)
  ) i_iobuf_bd (
    .dio_t (gpio_t[14:0]),
    .dio_i (gpio_o[14:0]),
    .dio_o (gpio_i[14:0]),
    .dio_p (gpio_bd));

  assign gpio_i[31:15] = gpio_o[31:15];
  assign gpio_i[63:60] = gpio_o[63:60];

  system_wrapper i_system_wrapper (
    .dac_fifo_bypass (gpio_o[60]),
    .adc_fir_filter_active (gpio_o[61]),
    .dac_fir_filter_active (gpio_o[62]),
    .ddr_addr (ddr_addr),
    .ddr_ba (ddr_ba),
    .ddr_cas_n (ddr_cas_n),
    .ddr_ck_n (ddr_ck_n),
    .ddr_ck_p (ddr_ck_p),
    .ddr_cke (ddr_cke),
    .ddr_cs_n (ddr_cs_n),
    .ddr_dm (ddr_dm),
    .ddr_dq (ddr_dq),
    .ddr_dqs_n (ddr_dqs_n),
    .ddr_dqs_p (ddr_dqs_p),
    .ddr_odt (ddr_odt),
    .ddr_ras_n (ddr_ras_n),
    .ddr_reset_n (ddr_reset_n),
    .ddr_we_n (ddr_we_n),
    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
    .fixed_io_mio (fixed_io_mio),
    .fixed_io_ps_clk (fixed_io_ps_clk),
    .fixed_io_ps_porb (fixed_io_ps_porb),
    .fixed_io_ps_srstb (fixed_io_ps_srstb),
    .gpio_i (gpio_i),
    .gpio_o (gpio_o),
    .gpio_t (gpio_t),
    .iic_main_scl_io (iic_scl),
    .iic_main_sda_io (iic_sda),
    .rx_data_0_n (rx_data_n[0]),
    .rx_data_0_p (rx_data_p[0]),
    .rx_data_1_n (rx_data_n[1]),
    .rx_data_1_p (rx_data_p[1]),
    .rx_data_2_n (rx_data_n[2]),
    .rx_data_2_p (rx_data_p[2]),
    .rx_data_3_n (rx_data_n[3]),
    .rx_data_3_p (rx_data_p[3]),
    .rx_ref_clk_0 (ref_clk1),
    .rx_ref_clk_2 (ref_clk1),
    .rx_sync_0 (rx_sync),
    .rx_sync_2 (rx_os_sync),
    .rx_sysref_0 (sysref),
    .rx_sysref_2 (sysref),
    .spi0_clk_i (spi_clk),
    .spi0_clk_o (spi_clk),
    .spi0_csn_0_o (spi_csn_ad9528),
    .spi0_csn_1_o (spi_csn_ad9371),
    .spi0_csn_2_o (),
    .spi0_csn_i (1'b1),
    .spi0_sdi_i (spi_miso),
    .spi0_sdo_i (spi_mosi),
    .spi0_sdo_o (spi_mosi),
    .spi1_clk_i (1'd0),
    .spi1_clk_o (),
    .spi1_csn_0_o (),
    .spi1_csn_1_o (),
    .spi1_csn_2_o (),
    .spi1_csn_i (1'b1),
    .spi1_sdi_i (1'd0),
    .spi1_sdo_i (1'd0),
    .spi1_sdo_o (),
    .tx_data_0_n (tx_data_n[0]),
    .tx_data_0_p (tx_data_p[0]),
    .tx_data_1_n (tx_data_n[1]),
    .tx_data_1_p (tx_data_p[1]),
    .tx_data_2_n (tx_data_n[2]),
    .tx_data_2_p (tx_data_p[2]),
    .tx_data_3_n (tx_data_n[3]),
    .tx_data_3_p (tx_data_p[3]),
    .tx_ref_clk_0 (ref_clk1),
    .tx_sync_0 (tx_sync),
    .tx_sysref_0 (sysref),
    .ref_clk (ref_clk1_bufg));

endmodule

    

    


    

      

    1. 

      Generated the bitstream + XSA
      

      2. 

    2. 

      Built PetaLinux:
      

        

      • 

        Used device-tree approach similar to zc706 project
        

        • 

      • 

        Generated BOOT files (BOOT.BIN, image.ub, etc.)
        

        • 

      

      3. 

    3. 

      Linux boots fine and the drivers probe:
      

        

      • 

        axi-jesd204-rx, axi-jesd204-tx
        

        • 

      • 

        axi-adxcvr-{tx,rx,rx-os}
        

        • 

      • 

        ad9371-phy appears in IIO
        

        • 

      

      4. 

    

    3) Current problem
    

    



    
    
    
        Fullscreen
        4812.Linux_logs.txt
        Download
    
    
    
    of-fpga-region fpga-full: FPGA Region probed
axi-jesd204-rx 44aa0000.axi-jesd204-rx: AXI-JESD204-RX (1.07.a) at 0x44AA0000. Encoder 8b10b, width 4/4, lanes 2, jesd204-fsm.
axi-jesd204-rx 44ab0000.axi-jesd204-rx: AXI-JESD204-RX (1.07.a) at 0x44AB0000. Encoder 8b10b, width 4/4, lanes 2, jesd204-fsm.
axi-jesd204-tx 44a90000.axi-jesd204-tx: AXI-JESD204-TX (1.06.a) at 0x44A90000. Encoder 8b10b, width 4/4, lanes 4, jesd204-fsm.
ad9371 spi0.1: ad9371_probe : enter
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition initialized -> probed
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition initialized -> probed
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition initialized -> probed
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition probed -> initialized
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition probed -> initialized
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition probed -> initialized
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition initialized -> probed
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition initialized -> probed
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition initialized -> probed
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition probed -> idle
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition probed -> idle
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition probed -> idle
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_pre_setup -> clk_sync_stage1
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_pre_setup -> clk_sync_stage1
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_pre_setup -> clk_sync_stage1
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage1 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition clk_sync_stage1 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition clk_sync_stage1 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage3
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition clk_sync_stage2 -> clk_sync_stage3
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage3
axi_adxcvr_drv 44a80000.axi-adxcvr-tx: QPLL TX Unlocked Error: 10
axi_adxcvr_drv 44a80000.axi-adxcvr-tx: QPLL TX Unlocked Error: 10
axi-jesd204-tx 44a90000.axi-jesd204-tx: axi_jesd204_tx_jesd204_link_setup: Link0 enable lane clock failed (-5)
jesd204: /fpga-axi@0/axi-jesd204-tx@44a90000,jesd204:4,parent=44a90000.axi-jesd204-tx: JESD204[0:0] In link_setup got error from cb: -5
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: Rolling back from 'clk_sync_stage3', got error -5
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition clk_sync_stage3 -> link_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition clk_sync_stage3 -> link_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage3 -> link_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_setup -> clk_sync_stage3
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_setup -> clk_sync_stage3
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_setup -> clk_sync_stage3
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition clk_sync_stage3 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition clk_sync_stage3 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage3 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage1
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition clk_sync_stage2 -> clk_sync_stage1
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage1
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition clk_sync_stage1 -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition clk_sync_stage1 -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage1 -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_pre_setup -> link_supported
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_pre_setup -> link_supported
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_pre_setup -> link_supported
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition idle -> initialized
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition idle -> initialized
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition idle -> initialized
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition initialized -> probed
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition initialized -> probed
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition initialized -> probed
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition probed -> idle
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition probed -> idle
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition probed -> idle
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_pre_setup -> clk_sync_stage1
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_pre_setup -> clk_sync_stage1
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_pre_setup -> clk_sync_stage1
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage1 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition clk_sync_stage1 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition clk_sync_stage1 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage3
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition clk_sync_stage2 -> clk_sync_stage3
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage3
axi_adxcvr_drv 44a80000.axi-adxcvr-tx: QPLL TX Unlocked Error: 10
axi_adxcvr_drv 44a80000.axi-adxcvr-tx: QPLL TX Unlocked Error: 10
axi-jesd204-tx 44a90000.axi-jesd204-tx: axi_jesd204_tx_jesd204_link_setup: Link0 enable lane clock failed (-5)
jesd204: /fpga-axi@0/axi-jesd204-tx@44a90000,jesd204:4,parent=44a90000.axi-jesd204-tx: JESD204[0:0] In link_setup got error from cb: -5
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: Rolling back from 'clk_sync_stage3', got error -5
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition clk_sync_stage3 -> link_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition clk_sync_stage3 -> link_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage3 -> link_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_setup -> clk_sync_stage3
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_setup -> clk_sync_stage3
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_setup -> clk_sync_stage3
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition clk_sync_stage3 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition clk_sync_stage3 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage3 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage1
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition clk_sync_stage2 -> clk_sync_stage1
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage1
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition clk_sync_stage1 -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition clk_sync_stage1 -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage1 -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_pre_setup -> link_supported
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_pre_setup -> link_supported
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_pre_setup -> link_supported
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition idle -> initialized
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition idle -> initialized
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition idle -> initialized
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition initialized -> probed
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition initialized -> probed
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition initialized -> probed
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition probed -> idle
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition probed -> idle
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition probed -> idle
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_pre_setup -> clk_sync_stage1
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_pre_setup -> clk_sync_stage1
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_pre_setup -> clk_sync_stage1
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage1 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition clk_sync_stage1 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition clk_sync_stage1 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage3
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition clk_sync_stage2 -> clk_sync_stage3
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage3
axi_adxcvr_drv 44a80000.axi-adxcvr-tx: QPLL TX Unlocked Error: 10
axi_adxcvr_drv 44a80000.axi-adxcvr-tx: QPLL TX Unlocked Error: 10
axi-jesd204-tx 44a90000.axi-jesd204-tx: axi_jesd204_tx_jesd204_link_setup: Link0 enable lane clock failed (-5)
jesd204: /fpga-axi@0/axi-jesd204-tx@44a90000,jesd204:4,parent=44a90000.axi-jesd204-tx: JESD204[0:0] In link_setup got error from cb: -5
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: Rolling back from 'clk_sync_stage3', got error -5
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition clk_sync_stage3 -> link_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition clk_sync_stage3 -> link_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage3 -> link_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_setup -> clk_sync_stage3
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_setup -> clk_sync_stage3
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_setup -> clk_sync_stage3
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition clk_sync_stage3 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition clk_sync_stage3 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage3 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage1
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition clk_sync_stage2 -> clk_sync_stage1
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage1
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition clk_sync_stage1 -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition clk_sync_stage1 -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage1 -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_pre_setup -> link_supported
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_pre_setup -> link_supported
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_pre_setup -> link_supported
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition idle -> initialized
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition idle -> initialized
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition idle -> initialized
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition initialized -> probed
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition initialized -> probed
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition initialized -> probed
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition probed -> idle
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition probed -> idle
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition probed -> idle
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition idle -> device_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition device_init -> link_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_init -> link_supported
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_supported -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_pre_setup -> clk_sync_stage1
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_pre_setup -> clk_sync_stage1
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_pre_setup -> clk_sync_stage1
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage1 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition clk_sync_stage1 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition clk_sync_stage1 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage3
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition clk_sync_stage2 -> clk_sync_stage3
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage3
axi_adxcvr_drv 44a80000.axi-adxcvr-tx: QPLL TX Unlocked Error: 10
axi_adxcvr_drv 44a80000.axi-adxcvr-tx: QPLL TX Unlocked Error: 10
axi-jesd204-tx 44a90000.axi-jesd204-tx: axi_jesd204_tx_jesd204_link_setup: Link0 enable lane clock failed (-5)
jesd204: /fpga-axi@0/axi-jesd204-tx@44a90000,jesd204:4,parent=44a90000.axi-jesd204-tx: JESD204[0:0] In link_setup got error from cb: -5
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: Rolling back from 'clk_sync_stage3', got error -5
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition clk_sync_stage3 -> link_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition clk_sync_stage3 -> link_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage3 -> link_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_setup -> clk_sync_stage3
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_setup -> clk_sync_stage3
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_setup -> clk_sync_stage3
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition clk_sync_stage3 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition clk_sync_stage3 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage3 -> clk_sync_stage2
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage1
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition clk_sync_stage2 -> clk_sync_stage1
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage1
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition clk_sync_stage1 -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition clk_sync_stage1 -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage1 -> link_pre_setup
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_pre_setup -> link_supported
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_pre_setup -> link_supported
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_pre_setup -> link_supported
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_supported -> link_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_init -> device_init
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:2] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:1] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition device_init -> idle
jesd204: /axi/spi@e0006000/ad9371-phy@1,jesd204:1,parent=spi0.1: FSM completed with error -5
cf_axi_dds 44a04000.axi-ad9371-tx-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.02.b) at 0x44A04000 mapped to 0x(ptrval), probed DDS AD9371
cf_axi_adc 44a00000.axi-ad9371-rx-hpc: ADI AIM (10.03.) at 0x44A00000 mapped to 0x(ptrval) probed ADC AD9371 as MASTER
input: gpio_keys as /devices/soc0/gpio_keys/input/input0
of_cfs_init
of_cfs_init: OK

    

    


    

    The JESD link never comes up. I get errors like:
    

      

    • 

      axi_adxcvr_drv 44a80000.axi-adxcvr-tx: CPLL TX Unlocked Error: 10
       (sometimes it shows QPLL depending on build/config)
      

      • 

    • 

      axi-jesd204-tx ... Link0 enable lane clock failed (-5)
      

      • 

    • 

      JESD FSM rolls back during clk_sync_stage3 / link_setup
      

      • 

    

    Also:
    

      

    • 

      Measured Link Clock: off
      

      • 

    • 

      Link is disabled
      

      • 

    • 

      RX lanes stay CGS state: INIT and Initial Frame Synchronization: No
      

      • 

    

    4) Debugging steps already tried
    

    A) Verified AD9528 IIO nodes exist
    

    I can read the AD9528 output frequencies from sysfs, for example:
    

      

    • 

      out_altvoltage1_FMC_CLK_frequency = 122880000 (default)
      

      • 

    • 

      out_altvoltage13_DEV_CLK_frequency = 122880000
      

      • 

    • 

      SYSREF nodes exist and show 60000 (60 kHz)
      

      • 

    

    B) Tested changing FMC_CLK frequency
    

    I tried to write other clock rates into:
    

      

    • 

      /sys/bus/iio/devices/iio:deviceX/out_altvoltage1_FMC_CLK_frequency
       and then echo 1 > sync_dividers.
      

      • 

    

    Some values are accepted (e.g., 153.6 MHz, 245.76 MHz, 307.2 MHz), but the JESD TX still fails with the same CPLL/QPLL TX Unlocked Error and enable lane clock failed.
    

    C) Checked Linux clock framework
    

    /sys/kernel/debug/clk/clk_summary shows ad9528-1_out1 and also clocks like tx_out_clk, tx_gt_clk, etc., but when the failure happens, the lane clock is never established and JESD stays disabled.
    

    D) Tried reset sequencing / re-enabling drivers
    

      

    • 

      Forced ensm_mode=radio_off
      

      • 

    • 

      Disabled/enabled JESD cores (echo 0/1 > .../enable)
      

      • 

    • 

      Disabled/enabled transceiver cores (axi-adxcvr)
      

      • 

    • 

      Unbind/bind platform drivers
      

      • 

    

    The failure persists.
    

    E) Vivado timing / clock period constraints
    

    I also adjusted create_clock constraints for ref clocks (example: 8.0 ns vs 8.138 ns) but this does not fix the issue. The failure appears hardware/clocking related (PLL not locking).
    

    5) My understanding / question
    

    My understanding is:
    

    AD9528 FMC_CLK → goes through FMC → arrives to FPGA pins ref_clk*_p/n → becomes GTREFCLK → used by Xilinx GTX QPLL→ creates TX serial clock → provides lane_clk for AXI-JESD204-TX.
    

    So the message axi_adxcvr... CPLL/QPLL TX Unlocked is coming from the FPGA transceiver PLL not locking.
    

    Question:
     What are the most likely causes for GTX QPLL not locking in this porting case?
    

    Specifically, I would like guidance on what to verify first:
    

      

    • 

      Refclk frequency mismatch vs the GTX configuration / JESD lane rate
      

      • 

    • 

      Wrong refclk pin mapping / IBUFDS_GTE2 usage / polarity issues
      

      • 

    • 

      Any required constraints or resets for GTX reference clocks
      

      • 

    • 

      Any known requirements in the zc706 design (Si5324/clocking assumptions) that do not apply directly to ADRV9371 FMC clocking
      

      • 

    
			
    
			
									
		                                 
    Thread Notes  
    
                
    
        
                                        
                        

    
    
                                            
                 Clock Generation Devices
                
                                                    
                 Clock Generation and Distribution
                
                                                    
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                 adrv9371
                
                                                    
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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Feb 9, 2026 7:34 AM
            
            
						
			            		
      
		
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      Hello,
      

      At first glance this looks like a ref_clk or xcvr params issue. The best way to debug it is to find the trx0_ad9371 node in the device tree and add the following line: 
      jesd204-ignore-errors;

      

      This will let the jesd204-fsm continue despite errors which is useful for debugging, otherwise the link will reset and that's why you see the link as disabled and measured clock off.
      

      Best regards,
      Andrei
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

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                on Feb 12, 2026 6:24 AM
            
            
						
			            		
        
		
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        Hello everyone,
        

        I would like to share an update and ask for guidance regarding my AD9371 setup.
        

        First, I was able to resolve the GTX QPLL not locking issue. The problem was related to the FMC clock routing. After ensuring that the FMC_HPC_GBTCLK1_M2C_P pin was correctly connected and driven with the proper reference clock, the QPLL locked successfully and the JESD link came up properly.
        

        Now I am facing a different issue related to the AD9371 Filter Wizard configuration.
        

        I am trying to generate a profile with an IQ sample rate of 30.72 MHz, since I plan to use this board for LTE with srsRAN, which requires 30.72 MSPS for 20 MHz LTE bandwidth.
        

        However, when I configure the Filter Wizard for 30.72 MHz, I receive the following error:
        

        

        “Tx 4x PFIR interpolation is not currently supported”
        

        

        It appears that the wizard automatically selects 4× interpolation in the TX PFIR stage, but this mode is not supported by the AD9371 hardware.
        

        My questions are:
        

          

        1. 

          What is the correct way to generate a valid 30.72 MHz profile for LTE operation?
          

          2. 

        2. 

          Which interpolation/decimation settings should be used in TX and RX to achieve 30.72 MSPS without triggering the 4× PFIR limitation?
          

          3. 

        3. 

          Is there a recommended reference profile for LTE 20 MHz operation with AD9371?
          

          4. 

        

        My goal is to meet the LTE sampling requirements for srsRAN while maintaining a valid and stable AD9371 clock configuration.
        

        Any guidance would be greatly appreciated.
        

        Thank you.
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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        •  Analog Employees  
        
            
						
                            
            
            				
            
                on Feb 16, 2026 5:18 AM
            
            
												
						in reply to Danial25548
					
										
			            		
        
		
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        I moved it to the Support AD9371/AD9375  forum. Someone from that forum may be able to help you.
        

        Regards,
        

        Elena
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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        •  Analog Employees  
        
            
						
                            
            
            				
            
                on Feb 17, 2026 7:52 AM
            
            
						
			            		
        
		
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        Danial25548 said:
        “Tx 4x PFIR interpolation is not currently supported”
        

        There is no plan to support 4x interpolation.
        

         Filter Wizard v1.4 - AD9371 
        

         Operate AD937X TX/RX with 61.44MSPS/30.72MSPS 
        

        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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                on Feb 18, 2026 6:23 AM
            
            
						
			            		
          
		
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          Hi all, I’m working with an ADRV9371 and trying to integrate it with srsRAN LTE. 
          From what I understand, the AD9371 profile/filter configuration has minimum supported baseband sample rates, so I can’t configure: TX input sample rate below 61.44 MSPS RX input sample rate below 30.72 MSPS 
          My question is: How can I integrate ADRV9371 with srsRAN for different LTE bandwidths, since LTE requires lower baseband sample rates such as 1.92, 3.84, 7.68, 15.36, and 30.72 MSPS (depending on the bandwidth)? If anyone has guidance on the recommended approach (e.g., keeping the RFIC at a fixed supported rate and doing interpolation/decimation in FPGA/host, or any known working configuration), I’d really appreciate it.
          
			
          

		
			
	      

		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

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          •  Analog Employees  
          
            
						
                            
            
            				
            
                on Feb 23, 2026 12:04 AM
            
            
						
			            		
          
		
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          This is not possible in AD9371. May be you can try up-sampling at FPGA  to use the sampling rate as per your requirement . 
          
			
          

		
			
	      

		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

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                on Mar 3, 2026 2:07 PM
            
            
												
						in reply to vanitha
					
										
			            		
            
		
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            Hi all,
            

            Thanks for the previous clarification that AD9371 can’t directly run at the LTE baseband rates (e.g., 7.68/15.36 MSPS) and that up-sampling in FPGA is the recommended direction.
            

            I have a follow-up question to make sure I’m not misunderstanding JESD vs. the RFIC’s internal constraints:
            

              

            1. 

              If I reduce the JESD lane count (L) in the HDL/device-tree (e.g., TX/RX/ORX to L=1), does that actually allow the AD9371 to operate at a lower baseband sample rate?
              

              As a concrete example, I did the JESD lane-rate math for targeting 7.68 MSPS assuming (M=4 converters, NP=16, 8b/10b, S=1) and a single lane (L=1):
              

              Lane Rate = 7.68 MSPS × M(4) × NP(16) × (10/8) ÷ L(1)
              = 614.4 Mb/s
              

              This looks like a reasonable lane rate from a JESD bandwidth point of view, but I’m not sure whether the AD9371 will accept a profile with TX/RX IQ rates that low in the first place.
              

              So the core question is: Is lowering L (number of lanes) a valid way to reduce the AD9371’s required sample rate, or must the AD9371 still run at its minimum supported baseband rate and any LTE-rate operation must be done via interpolation/decimation outside the RFIC (FPGA/host)?
              

              Any guidance on the correct interpretation (and any known supported low-rate modes, if they exist) would be very helpful.
              

              Best regards,
              

              2. 

            
			
            

		
			
	      

		
		
	
            
	
            
		
            
			
		
            
	
            
	
            
		
						
						
				
						
				
				
		
		
            
			
		
            
	
            

            

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            •  Analog Employees  
            
            
						
                            
            
            				
            
                on Mar 4, 2026 12:10 PM
            
            
						
			            		
            
		
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            It is not possible to configure with 7.68Msps and the min sampling rate supported is 30Msps . 
            

             
            

            wiki.analog.com/.../filters
            
			
            

		
			
	      

		
		
	
            
	
            
		
            
			
		
            
	
            
	
            
		
						
				
						
						
				
				
		
		
            
			
		
            
	
            

            

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