Category: Software
Product Number: AD9375
Hi,
I am using AXI QuadSPI IP (FPGA ZC706) as SPI MAIN to connect to AD9375.
Unfortunately, AXI QuadSPI's ChipSelect cannot be manually/forcefully controlled. So, SPI CS will be a LOW for a 32-bit MOSI, and then it will go HIGH. The process repeats until every 32 bit word in DTR FIFO is sent.
For this AXI QuadSPI IP model, if I want to WRITE "SPI Register 000" with value "0x18", on a MSB First Method, would I need to send 0x00001800, or would I need to send 0x00000018 ??
Will the procedure disturb the next 32-bit word, which I would need WRITE Register 001 with 0x80 ?? Can you please help with how to synchronize the 24-bit word that AD9375 is expecting?
AXI QuadSPI Document - https://docs.amd.com/r/en-US/pg153-axi-quad-spi
- Standard SPI, 1 SPI Subordinate connected (AD9375)
- Transaction Width = 32
- Frequency Div = 256
- Clock for AXI QUAD SPI = 62.5 MHz
