ARM checksum fail after clock update

Can you share us the error log where issue is seen ?

Which SW version are you using ? Are you using Linux or No-Os drivers for initializing the chip?

Anpnwan said:

I have probed SPI clock for both 153.6 and 122.88 which is 3.7Mhz in both the cases ? 

What is the SPI clock (spiClkFreq_Hz) configured in your SPI settings ? In default it should be 25MHz.

Can you probe the device clock  and see if it has changed from 153.6MHz to 122.88MHz in the chip?

Hi,

vanitha said:

Can you share us the error log where issue is seen ?

We are using No-Os drivers for initialization. There is no error log except verifychecksum function is returning error.

Mykonos version I'm using is 1.4.0.3546

Anpnwan said:

Mykonos API version: 1.4.0.3546

vanitha said:

What is the SPI clock (spiClkFreq_Hz) configured in your SPI settings ? In default it should be 25MHz.

We are not setting spiClkFreq in spisettings of AD9528 and AD9371 explicitly.  when we probed for 153.6MHz and 122.88Mhz, SPI clock in both the cases is 3.7Mhz.  But in case of 122.88 MHz ARM Checksum is failing.

Calibrations and PLLs are locked successfully in both the cases. 

vanitha said:

Can you probe the device clock  and see if it has changed from 153.6MHz to 122.88MHz in the chip?

Yes I probed device clock, FPGA aux clock which is 122.88MHz. The SYSref is 120KHz .

Any help is appreciated

Thank you 

Which custom FPGA are you using? Are you seeing this issue in single or multiple boards?

Anpnwan said:

We are using No-Os drivers for initialization. There is no error log except verifychecksum function is returning error.

Can you please share the snippet of the error seen?

Anpnwan said:

We are not setting spiClkFreq in spisettings of AD9528 and AD9371 explicitly. 

We usually set the SPI settings for AD9528 and AD9371. See below for details.

https://wiki.analog.com/resources/eval/user-guides/mykonos/no-os-setup

Can you please try writing and reading back from the scratch pad register and see if SPI interface is fine.

Anpnwan said:

when we probed for 153.6MHz and 122.88Mhz, SPI clock in both the cases is 3.7Mhz. 

Can you try increasing the SPI clock and see if you don't see any issue.

Please refer to the initialization sequence in UG992-Page61  for more details.

vanitha said:

custom FPGA

I'm using Polarfire FPGA 

vanitha said:

Are you seeing this issue in single or multiple boards?

Yes every board I tested  had same issue.

vanitha said:

We usually set the SPI settings for AD9528 and AD9371. See below for details.

I tried setting SPI clock but no change in clock and ARM checksum (it is still showing ARM checksum failure). SPI clock is same(3.7MHz) in both the cases (ARM checksum success and ARM checksum failure). So I think it might not be problem with SPI clock.

Could you please tell the address of scratchpad register. I tried reading Device ID (at 0x4) address using SPI, it is matching with both ARM checksum failure and checksum  success case

May I know how ARM bin file is generated? How can I generate my own ARM bin file ? 

Could you please point me to descriptions of SPI registers on AD9371. I can only see SPI registers in mykonos_macros file but there is no explanation about what each bit in registers do.  

What registers I need to write to enable ARM clock in order to  initialise ARM and load ARM bin using SPI without JESD setup (i,e skipping steps mentioned in PAGE 15 API sequence). I would like to enable ARM and load ARM binary and do checksum verification without setting up RX, TX and other paths in AD9371.

Thanks

Anpnwan said:

Could you please tell the address of scratchpad register.

Register 0x00A is the scratch pad register. You can write and readback from this register to verify SPI.

Which profile are you using ? Is it generated with device clock of 122.88MHz?

Headless.c has the implementation of the main.c function . You can omit the JESD Bringup section and proceed with the initialization.

https://github.com/analogdevicesinc/no-OS/blob/main/projects/ad9371/src/app/headless.c

Anpnwan said:

I would like to enable ARM and load ARM binary and do checksum verification without setting up RX, TX and other paths in AD9371.

You can initialize and load the ARM binaries, its already part of the initialization sequence.

Can you please share us the error snippet/log where the function is returning error.

HI ,

Thank you for the reply. 

vanitha said:

Which profile are you using ? Is it generated with device clock of 122.88MHz?

Yes the profile is generated using 122.88. 

I think  ARM checksum failure has to do with FPGA transceiver configuration/clocks rather than software or SPI clock. Because SPI clock is same in working profile (which is 153.6) and non-working profile  (which is 122.88) , also we probed clocks generated by ad9528 which is correctly generating 122.88MHz (also 120KHz sysref).

Major change in non-working design is in data rate/clock setting for transceiver which we set according to 122.88 MHz .

Do you think transceiver setting could be reason behind ARM checksum failure ? As this is the data-path not the control-path (SPI lines) I'm not sure how it affects ARM code loaded through SPI.

Thanks

The issue could be related to the clock settings. 

https://github.com/analogdevicesinc/no-OS/blob/main/projects/ad9371/src/app/myk.c

Is the profile with updated clock settings generated from the Mykonos profile wizard and then used for the testing?

VCO dividers will be taken care internally if you generate the profile through AD9371 profile wizard.

Have you tried probing the device clock at the transceiver output, Is it as expected ?

Please share us the error log where you see the ARM checksum failure.