Tx spur at 3440.6MHz(n78 PA), 3686.4MHz (n78 PA), 4915.3MHz(n79 PA)

Hi

I have two costom boards with n78 and n79 PA.

Is there any suggestion to fix spur? thanks

The n78 have two fixed spurs even I change frequency, atten, bandwidth, ref_clock(for LO).

spur：3440.6MHz=122.88*28，3686.4MHz=122.88*30

The n79.

spur：4915.3MHz=122.88*40

JESD setting

ad9528 setting, The device clock and sysref clock are 122.88MHz.

/* Ref = 30.72MHz on REFA (SATA)  Lock Mask = 0xe7 */
static const uint16_t ad9528_RefA_30M72_regs[][2] =
{
    { 0x00, 0x3c},
    { 0x01, 0x80},
    { 0x100, 0x01},  /* RefA div = 1 */
    { 0x101, 0x00},
    { 0x102, 0x01},
    { 0x103, 0x00},
    { 0x104, 0x04},  /* N1 div = 4    122.88MHz / 4 = 30.72MHz */
    { 0x105, 0x00},
    { 0x106, 0x0a},  /* PLL1 Charge Pump current: 10uA */
    { 0x107, 0x03},  /* Auto holdover */
    { 0x108, 0x08},  /* REFA on, single ended */
    { 0x109, 0x04},  /* 4: PPL1  from VCXO, 0: PLL1 from PPL2 output */
    { 0x10a, 0x02},  /* Ref = REFA, tristate holdover */
    { 0x10b, 0x00},
    { 0x200, 0xe6},
    { 0x201, 0x87},  /* CAL div = 30 */
    { 0x202, 0x03},
    { 0x203, 0x00},
    { 0x204, 0x03},  /* M1 = 3 */
    { 0x205, 0x2a},  /* PLL2 loop filter: 900R/2500R/16pF */
    { 0x206, 0x00},
    { 0x207, 0x00},
    { 0x208, 0x09},  /* N2 Div = 10 */
    { 0x209, 0x00},
    { 0x300, ADSYSREF_OUT}, /* OUT0: FPGA0_SYSREF */
    { 0x301, 0x00},
    { 0x302, 0x09},
    { 0x303, ADDEVCLK_OUT}, /* OUT1: FPGA0_DEV_CLK */
    { 0x304, 0x00},
    { 0x305, 0x09},
    { 0x306, ADDEVCLK_OUT}, /* OUT2: AD_A_DEV_CLK */
    { 0x307, 0x00},  /* 0x40 LVDS Boost */
    { 0x308, 0x09},
    { 0x309, ADDEVCLK_OUT}, /* OUT3: AD_B_DEV_CLK */
    { 0x30a, 0x00},  /* 0x40 LVDS Boost */
    { 0x30b, 0x09},
    { 0x30c, ADSYSREF_OUT}, /* OUT4: AD_A_SYSREF */
    { 0x30d, 0x00 + ADSYSREF_COFF_A},
    { 0x30e, 0x09},
    { 0x30f, ADDEVCLK_OUT}, /* OUT5: FPGA1_DEV_CLK */
    { 0x310, 0x00},
    { 0x311, 0x09},
    { 0x312, ADSYSREF_OUT}, /* OUT6: FPGA1_SYSREF */
    { 0x313, 0x00},
    { 0x314, 0x09},
    { 0x315, ADSYSREF_OUT}, /* OUT7: AD_B_SYSREF */
    { 0x316, 0x00 + ADSYSREF_COFF_B},
    { 0x317, 0x09},
    { 0x318, ADDEVCLK_OUT},  /* OUT8: CLKOUT0 */
    { 0x319, 0x00},
    { 0x31a, 0x09},   // 0x01 to output 614.4 MHz */
    { 0x31b, ADDEVCLK_OUT},  /* OUT9: REFOUT, N/A */
    { 0x31c, 0x00},
    { 0x31d, 0x09},
    { 0x31e, ADDEVCLK_OUT},  /* OUT10: CLKOUT1 */
    { 0x31f, 0x00},
    { 0x320, 0x09},
    { 0x321, ADDEVCLK_OUT},  /* OUT11: CLKOUT2 */
    { 0x322, 0x00},
    { 0x323, 0x09},
    { 0x324, ADDEVCLK_OUT},  /* OUT12: N/A */
    { 0x325, 0x00},
    { 0x326, 0x09},
    { 0x327, ADDEVCLK_OUT},  /* OUT13: N/A */
    { 0x328, 0x00},
    { 0x329, 0x09},
    { 0x32a, 0x00},
    { 0x32b, 0x00},
    { 0x32c, 0x00},
    { 0x32d, 0x00},  /* SYSREF resampling Bypass 0xA2 */
    { 0x32e, 0x00},  /* SYSREF resampling Bypass 0x01 */
    { 0x400, 0x00},
    { 0x401, 0x08},  /* SYSREF Div 0x800 => 122.88/(2*2048) => 30KHz (2 => 122.88/1024 => 120KHz) */
    { 0x402, 0x00},
    { 0x403, 0x80},
    { 0x404, 0x04},
    { 0x500, 0x10},
    { 0x501, 0x00}, /*  Default: All power UP (else SYSREF does not work)*/
    { 0x502, 0x32}, /* Power down out 9, 12 and 13 */
    { 0x503, 0xff},
    { 0x504, 0xcd}, /* Power down out 9, 12 and 13 */
    { 0x505, 0x07},
    { 0x506, 0x01},
    { 0x507, 0x0c},

    { 0x0F, 0x01},   /* Update */
};

ad9528_profile ad9528_RefA_30M72_1_profile =
{
    "RefA 30.72MHz",
    30720000,
    ad9528_RefA_30M72_regs,
    ARRAY_SIZE(ad9528_RefA_30M72_regs),
    AD9528_REFB_SATA,
    AD9528_LOCK_REFA
};