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AD9371 Framer lane FIFO read/write pointer delta has changed

Category: Hardware
Product Number: AD9371

When we reinitialize our JESD interface using _jesdInit(), we see the Rx Framer status of 0x7e rather than 0x3e about 2% of the time, indicating that the "Framer lane FIFO read/write pointer delta has changed." I have seen a few other similar inquiries but have not seen a clear answer to those questions so I am posting this one. Also, I have looked over the JESD204B Debugging document but I don't see what is causing our problem. I would like to know: 1) What causes this error in the framer path, 2) Is this error clear-on-read or do we need to clear it another way, 3) Other questions submitted indicate that their link appears to be running fine when this error is indicated so what are the issues with continuing to use the link rather than clearing the error. BTW, the Xilinx JESD204B cores on the opposite side of the link do not show any errors. Any help would be appreciated. Thank you.

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  • Good to hear.  We've made some further progress on this issue. 

    We also moved the write to DESERIALIZER_SPECIAL out of mykonos.c.

    We were doing 3 Sys Ref Requests to the 9528 after the call to MYKONOS_enableMultichipSync now only doing 2.

    We also tweaked delays after resets to the various PLLs.

    We typically run 1000's of tunes and each time we tweaked something we got less and less errors.  Not sure we are at 100% success yet, but getting closer.