AD9375 SYNCOUT_B is from HI to Low, when change TXATT to 0dBFS from -2dBFS with 0dBFS digital input

sss@jpn said:

SYNCOUT_B is from HI to Low, when change TXATT to 0dBFS from -2dBFS with 0dBFS digital input.

Do you mean JESD is getting Reset ?

Is it custom board or evaluation board ?

Soft overload means , you will not see sudden clipping.

Hi Vinod - san,

Thank you for quick reply.

>Do you mean JESD is getting Reset ?

Yes, SYNCOUT_B status is change.

They say changed the TXATT setting only.

We wonder why it require the JESD reset.

We think that this issue is not related to monitoring the JESD204B link for running disparity errors.

Are there any factors that could be considered?

>Is it custom board or evaluation board ?

It's Evaliation boards.

ADRV9375-W/PCBZ + Aria 10 Development Kit

>Soft overload means , you will not see sudden clipping.

In this time, I understand the note is no relation.

Is it correct ?

Best regards,

sss

With attenuation change JESD will not reset. Only chance of this happening is variation in power supply when attenuation changes impacting JESD. I don't see this happening in evaluation board.

sss@jpn said:

>Soft overload means , you will not see sudden clipping.

In this time, I understand the note is no relation.

Is it correct ?

Yes this has no relation to issue seen.

Initial post mentions -2dBFS  , are they changing digital signal power at baseband. (FPGA) and not Tx attenuation ?

Can they share more details like log files or steps to recreate the issue.

Hi Vinod - san,

Here is customer evaluate details.

1.Each evaluation boards is ,
RFIC : ADRV9375-W/PCBZ
FPGA: Intel (Arria V ST Soc or Arria 10 GX , both happend)。
Setting to change is the TXATT only .

2.Phenomenon when changing the TXATT
note:The customer describes "SYNCOUTB0+/-" as "TXSYNC_B".
"SYNCOUTB0" = "TXSYNC_B"

When change to TXATT:-2dBFS >>>0dBFS, TXSYNC_B:H>>>L（repeat High and Low）
then,
When return to TXATT:0dBFS>>>-2dBFS, repeat High and Low continus.

Please check the attached file.

3.DAC (PA) output
CW 960MHz, Tx signal
TXATT = 0dB, IQ amplitude:-2dBFS, +26dBm output

When the Digital FS data fix (0dBFS), and the TXATT changing (2~11dB,1dB step)

When the TXATT fix (2dB), and the digital FS data changing (-2dBFS~-11dBFS,1dBFS step)

In the above two patterns, the DAC (PA) operates in a linear manner.
: If either TXATT or Digital FS data is not full scale.

When the TXATT (0dB), and the digital FS DATA (0dBFS)
Please refer to above 2.

>With attenuation change JESD will not reset. Only chance of this

>happening is variation in power supply when attenuation changes

>impacting JESD. I don't see this happening in evaluation board.

We realized that it was necessary to check the supply capability and transient response etc. of the power supply line at DAC FS output.
Can you give me some advice on checkpoints and notes on power supply lines ?

Best regards,
sss

You may need to add some high value capacitors (220 UF) on power lanes especially 1.8 V lanes (VDDA1P8_TX) and 1.3 V (VDDA1P3_RF_SYNTH, VDDA1P3_RX_TX )

Hi Vinod - san,

Thank you for very useful replly！

Our customer checked the power supply line again.

Then, when setting to the DAC FS output,

they confirmed that the power line was unstable !

Best regards,

sss