Setting AD9371 for 80MHz sampling clk

Here is .m file I sed to automate a setup (disabling TX_QEC_INIT Calibration & loading profile)

The first problem that needs to get addressed is the profile generation issue.

Modifying or fixing a profile by hand is a bad idea, there might be some constrains that are not met and thus the profile is generated the way it is.

Of course in case it's obviously buggy, fixing it does not mean it must work the way it's being modified.

The next issue is the failing TX QEC INIT calibration, which can be a result of an invalid profile.

Have you tried using a device clock of 80 MHz ?

Can you attach your modified devicetree dts?

I'll move this thread to the AD9371 design support forum for further inputs on the filter designer issue.

-Michael

For some reasons I cant’t copy a file to the post, so here is a text copy of .dts file:

/dts-v1/;

/ {

               #address-cells = <0x1>;

               #size-cells = <0x1>;

               model = "Altera SOCFPGA Arria 10";

               compatible = "altr,socfpga-arria10", "altr,socfpga";

               chosen {

                              bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p3 rw rootwait earlyprintk";

                              stdout-path = "serial0:115200n8";

               };

               aliases {

                              ethernet0 = "/soc/ethernet@ff800000";

                              serial0 = "/soc/serial1@ffc02100";

               };

               memory {

                              device_type = "memory";

                              reg = <0x0 0x40000000>;

               };

               cpus {

                              #address-cells = <0x1>;

                              #size-cells = <0x0>;

                              enable-method = "altr,socfpga-a10-smp";

                              cpu@0 {

                                             compatible = "arm,cortex-a9";

                                             device_type = "cpu";

                                             reg = <0x0>;

                                             next-level-cache = <0x1>;

                              };

                              cpu@1 {

                                             compatible = "arm,cortex-a9";

                                             device_type = "cpu";

                                             reg = <0x1>;

                                             next-level-cache = <0x1>;

                              };

               };

               intc@ffffd000 {

                              compatible = "arm,cortex-a9-gic";

                              #interrupt-cells = <0x3>;

                              interrupt-controller;

                              reg = <0xffffd000 0x1000 0xffffc100 0x100>;

                              linux,phandle = <0x2>;

                              phandle = <0x2>;

               };

               soc {

                              #address-cells = <0x1>;

                              #size-cells = <0x1>;

                              compatible = "simple-bus";

                              device_type = "soc";

                              interrupt-parent = <0x2>;

                              ranges;

                              amba {

                                             compatible = "simple-bus";

                                             #address-cells = <0x1>;

                                             #size-cells = <0x1>;

                                             ranges;

                                             pdma@ffda1000 {

                                                            compatible = "arm,pl330", "arm,primecell";

                                                            reg = <0xffda1000 0x1000>;

                                                            interrupts = <0x0 0x53 0x4 0x0 0x54 0x4 0x0 0x55 0x4 0x0 0x56 0x4 0x0 0x57 0x4 0x0 0x58 0x4 0x0 0x59 0x4 0x0 0x5a 0x4 0x0 0x5b 0x4>;

                                                            #dma-cells = <0x1>;

                                                            #dma-channels = <0x8>;

                                                            #dma-requests = <0x20>;

                                                            clocks = <0x3>;

                                                            clock-names = "apb_pclk";

                                                            microcode-cached;

                                                            linux,phandle = <0x1b>;

                                                            phandle = <0x1b>;

                                             };

                              };

                              base_fpga_region {

                                             #address-cells = <0x2>;

                                             #size-cells = <0x1>;

                                             compatible = "fpga-region", "simple-bus";

                                             fpga-mgr = <0x4>;

                                             ranges = <0x0 0x0 0xc0000000 0x20000000 0x1 0x0 0xff200000 0x200000>;

                                             bridge0@0x0 {

                                                            compatible = "simple-bus";

                                                            #size-cells = <0x1>;

                                                            #address-cells = <0x1>;

                                                            ranges = <0x0 0x0 0x0 0x20000000>;

                                                            mwipcore@0x00000000 {

                                                                           compatible = "mathworks,mwipcore-v3.00";

                                                                           reg = <0x0 0x10000>;

                                                                           #address-cells = <0x1>;

                                                                           #size-cells = <0x0>;

                                                                           mmrd-channel@0 {

                                                                                          reg = <0x0>;

                                                                                          compatible = "mathworks,mm-read-channel-v1.00";

                                                                                          mathworks,dev-name = "mmrd0";

                                                                           };

                                                                           mmwr-channel@1 {

                                                                                          reg = <0x1>;

                                                                                          compatible = "mathworks,mm-write-channel-v1.00";

                                                                                          mathworks,dev-name = "mmwr0";

                                                                           };

                                                            };

                                             };

                                             bridge1@0x1 {

                                                            compatible = "simple-bus";

                                                            #size-cells = <0x1>;

                                                            #address-cells = <0x1>;

                                                            ranges = <0x0 0x1 0x0 0x200000>;

                                             };

                              };

                              clkmgr@ffd04000 {

                                             compatible = "altr,clk-mgr";

                                             reg = <0xffd04000 0x1000>;

                                             clocks {

                                                            #address-cells = <0x1>;

                                                            #size-cells = <0x0>;

                                                            cb_intosc_hs_div2_clk {

                                                                           #clock-cells = <0x0>;

                                                                           compatible = "fixed-clock";

                                                                           linux,phandle = <0xd>;

                                                                           phandle = <0xd>;

                                                            };

                                                            cb_intosc_ls_clk {

                                                                           #clock-cells = <0x0>;

                                                                           compatible = "fixed-clock";

                                                                           linux,phandle = <0x6>;

                                                                           phandle = <0x6>;

                                                            };

                                                            f2s_free_clk {

                                                                           #clock-cells = <0x0>;

                                                                           compatible = "fixed-clock";

                                                                           linux,phandle = <0x7>;

                                                                           phandle = <0x7>;

                                                            };

                                                            osc1 {

                                                                           #clock-cells = <0x0>;

                                                                           compatible = "fixed-clock";

                                                                           clock-frequency = <0x17d7840>;

                                                                           linux,phandle = <0x5>;

                                                                           phandle = <0x5>;

                                                            };

                                                            main_pll {

                                                                           #address-cells = <0x1>;

                                                                           #size-cells = <0x0>;

                                                                           #clock-cells = <0x0>;

                                                                           compatible = "altr,socfpga-a10-pll-clock";

                                                                           clocks = <0x5 0x6 0x7>;

                                                                           reg = <0x40>;

                                                                           linux,phandle = <0x8>;

                                                                           phandle = <0x8>;

                                                                           main_mpu_base_clk {

                                                                                          #clock-cells = <0x0>;

                                                                                          compatible = "altr,socfpga-a10-perip-clk";

                                                                                          clocks = <0x8>;

                                                                                          div-reg = <0x140 0x0 0xb>;

                                                                                          linux,phandle = <0xb>;

                                                                                          phandle = <0xb>;

                                                                           };

                                                                           main_noc_base_clk {

                                                                                          #clock-cells = <0x0>;

                                                                                          compatible = "altr,socfpga-a10-perip-clk";

                                                                                          clocks = <0x8>;

                                                                                          div-reg = <0x144 0x0 0xb>;

                                                                                          linux,phandle = <0xe>;

                                                                                          phandle = <0xe>;

                                                                           };

                                                                           main_emaca_clk {

                                                                                          #clock-cells = <0x0>;

                                                                                          compatible = "altr,socfpga-a10-perip-clk";

                                                                                          clocks = <0x8>;

                                                                                          reg = <0x68>;

                                                                           };

                                                                           main_emacb_clk {

                                                                                          #clock-cells = <0x0>;

                                                                                          compatible = "altr,socfpga-a10-perip-clk";

                                                                                          clocks = <0x8>;

                                                                                          reg = <0x6c>;

                                                                           };

                                                                           main_emac_ptp_clk {

                                                                                          #clock-cells = <0x0>;

                                                                                          compatible = "altr,socfpga-a10-perip-clk";

                                                                                          clocks = <0x8>;

                                                                                          reg = <0x70>;

                                                                           };

                                                                           main_gpio_db_clk {

                                                                                          #clock-cells = <0x0>;

                                                                                          compatible = "altr,socfpga-a10-perip-clk";

                                                                                          clocks = <0x8>;

                                                                                          reg = <0x74>;

                                                                           };

                                                                           main_sdmmc_clk {

                                                                                          #clock-cells = <0x0>;

                                                                                          compatible = "altr,socfpga-a10-perip-clk";

                                                                                          clocks = <0x8>;

                                                                                          reg = <0x78>;

                                                                                          linux,phandle = <0x12>;

                                                                                          phandle = <0x12>;

                                                                           };

                                                                           main_s2f_usr0_clk {

                                                                                          #clock-cells = <0x0>;

                                                                                          compatible = "altr,socfpga-a10-perip-clk";

                                                                                          clocks = <0x8>;

                                                                                          reg = <0x7c>;

                                                                           };

                                                                           main_s2f_usr1_clk {

                                                                                          #clock-cells = <0x0>;

                                                                                          compatible = "altr,socfpga-a10-perip-clk";

                                                                                          clocks = <0x8>;

                                                                                          reg = <0x80>;

                                                                                          linux,phandle = <0x10>;

                                                                                          phandle = <0x10>;

                                                                           };

                                                                           main_hmc_pll_ref_clk {

                                                                                          #clock-cells = <0x0>;

                                                                                          compatible = "altr,socfpga-a10-perip-clk";

                                                                                          clocks = <0x8>;

                                                                                          reg = <0x84>;

                                                                           };

                                                                           main_periph_ref_clk {

                                                                                          #clock-cells = <0x0>;

                                                                                          compatible = "altr,socfpga-a10-perip-clk";

                                                                                          clocks = <0x8>;

                                                                                          reg = <0x9c>;

                                                                                          linux,phandle = <0x9>;

                                                                                          phandle = <0x9>;

                                                                           };

                                                            };

                                                            periph_pll {

                                                                           #address-cells = <0x1>;

                                                                           #size-cells = <0x0>;

                                                                           #clock-cells = <0x0>;

                                                                           compatible = "altr,socfpga-a10-pll-clock";

                                                                           clocks = <0x5 0x6 0x7 0x9>;

                                                                           reg = <0xc0>;

                                                                           linux,phandle = <0xa>;

                                                                           phandle = <0xa>;

                                                                           peri_mpu_base_clk {

                                                                                          #clock-cells = <0x0>;

                                                                                          compatible = "altr,socfpga-a10-perip-clk";

                                                                                          clocks = <0xa>;

                                                                                          div-reg = <0x140 0x10 0xb>;

                                                                                          linux,phandle = <0xc>;

                                                                                          phandle = <0xc>;

                                                                           };

                                                                           peri_noc_base_clk {

                                                                                          #clock-cells = <0x0>;

                                                                                          compatible = "altr,socfpga-a10-perip-clk";

                                                                                          clocks = <0xa>;

                                                                                          div-reg = <0x144 0x10 0xb>;

                                                                                          linux,phandle = <0xf>;

                                                                                          phandle = <0xf>;

                                                                           };

                                                                           peri_emaca_clk {

                                                                                          #clock-cells = <0x0>;

                                                                                          compatible = "altr,socfpga-a10-perip-clk";

                                                                                          clocks = <0xa>;

                                                                                          reg = <0xe8>;

                                                                           };

                                                                           peri_emacb_clk {

                                                                                          #clock-cells = <0x0>;

                                                                                          compatible = "altr,socfpga-a10-perip-clk";

                                                                                          clocks = <0xa>;

                                                                                          reg = <0xec>;

                                                                           };

                                                                           peri_emac_ptp_clk {

                                                                                          #clock-cells = <0x0>;

                                                                                          compatible = "altr,socfpga-a10-perip-clk";

                                                                                          clocks = <0xa>;

                                                                                          reg = <0xf0>;

                                                                           };

                                                                           peri_gpio_db_clk {

                                                                                          #clock-cells = <0x0>;

                                                                                          compatible = "altr,socfpga-a10-perip-clk";

                                                                                          clocks = <0xa>;

                                                                                          reg = <0xf4>;

                                                                           };

                                                                           peri_sdmmc_clk {

                                                                                          #clock-cells = <0x0>;

                                                                                          compatible = "altr,socfpga-a10-perip-clk";

                                                                                          clocks = <0xa>;

                                                                                          reg = <0xf8>;

                                                                                          linux,phandle = <0x13>;

                                                                                          phandle = <0x13>;

                                                                           };

                                                                           peri_s2f_usr0_clk {

                                                                                          #clock-cells = <0x0>;

                                                                                          compatible = "altr,socfpga-a10-perip-clk";

                                                                                          clocks = <0xa>;

                                                                                          reg = <0xfc>;

                                                                           };

                                                                           peri_s2f_usr1_clk {

                                                                                          #clock-cells = <0x0>;

                                                                                          compatible = "altr,socfpga-a10-perip-clk";

                                                                                          clocks = <0xa>;

                                                                                          reg = <0x100>;

                                                                                          linux,phandle = <0x11>;

                                                                                          phandle = <0x11>;

                                                                           };

                                                                           peri_hmc_pll_ref_clk {

                                                                                          #clock-cells = <0x0>;

                                                                                          compatible = "altr,socfpga-a10-perip-clk";

                                                                                          clocks = <0xa>;

                                                                                          reg = <0x104>;

                                                                           };

                                                            };

                                                            mpu_free_clk {

                                                                           #clock-cells = <0x0>;

                                                                           compatible = "altr,socfpga-a10-perip-clk";

                                                                           clocks = <0xb 0xc 0x5 0xd 0x7>;

                                                                           reg = <0x60>;

                                                                           linux,phandle = <0x15>;

                                                                           phandle = <0x15>;

                                                            };

                                                            noc_free_clk {

                                                                           #clock-cells = <0x0>;

                                                                           compatible = "altr,socfpga-a10-perip-clk";

                                                                           clocks = <0xe 0xf 0x5 0xd 0x7>;

                                                                           reg = <0x64>;

                                                                           linux,phandle = <0x14>;

                                                                           phandle = <0x14>;

                                                            };

                                                            s2f_user1_free_clk {

                                                                           #clock-cells = <0x0>;

                                                                           compatible = "altr,socfpga-a10-perip-clk";

                                                                           clocks = <0x10 0x11 0x5 0xd 0x7>;

                                                                           reg = <0x104>;

                                                            };

                                                            sdmmc_free_clk {

                                                                           #clock-cells = <0x0>;

                                                                           compatible = "altr,socfpga-a10-perip-clk";

                                                                           clocks = <0x12 0x13 0x5 0xd 0x7>;

                                                                           fixed-divider = <0x4>;

                                                                           reg = <0xf8>;

                                                                           linux,phandle = <0x16>;

                                                                           phandle = <0x16>;

                                                            };

                                                            l4_sys_free_clk {

                                                                           #clock-cells = <0x0>;

                                                                           compatible = "altr,socfpga-a10-perip-clk";

                                                                           clocks = <0x14>;

                                                                           fixed-divider = <0x4>;

                                                                           linux,phandle = <0x25>;

                                                                           phandle = <0x25>;

                                                            };

                                                            l4_main_clk {

                                                                           #clock-cells = <0x0>;

                                                                           compatible = "altr,socfpga-a10-gate-clk";

                                                                           clocks = <0x14>;

                                                                           div-reg = <0xa8 0x0 0x2>;

                                                                           clk-gate = <0x48 0x1>;

                                                                           linux,phandle = <0x3>;

                                                                           phandle = <0x3>;

                                                            };

                                                            l4_mp_clk {

                                                                           #clock-cells = <0x0>;

                                                                           compatible = "altr,socfpga-a10-gate-clk";

                                                                           clocks = <0x14>;

                                                                           div-reg = <0xa8 0x8 0x2>;

                                                                           clk-gate = <0x48 0x2>;

                                                                           linux,phandle = <0x17>;

                                                                           phandle = <0x17>;

                                                            };

                                                            l4_sp_clk {

                                                                           #clock-cells = <0x0>;

                                                                           compatible = "altr,socfpga-a10-gate-clk";

                                                                           clocks = <0x14>;

                                                                           div-reg = <0xa8 0x10 0x2>;

                                                                           clk-gate = <0x48 0x3>;

                                                                           linux,phandle = <0x1a>;

                                                                           phandle = <0x1a>;

                                                            };

                                                            mpu_periph_clk {

                                                                           #clock-cells = <0x0>;

                                                                           compatible = "altr,socfpga-a10-gate-clk";

                                                                           clocks = <0x15>;

                                                                           fixed-divider = <0x4>;

                                                                           clk-gate = <0x48 0x0>;

                                                                           linux,phandle = <0x24>;

                                                                           phandle = <0x24>;

                                                            };

                                                            sdmmc_clk {

                                                                           #clock-cells = <0x0>;

                                                                           compatible = "altr,socfpga-a10-gate-clk";

                                                                           clocks = <0x16>;

                                                                           clk-gate = <0xc8 0x5>;

                                                                           clk-phase = <0x0 0x87>;

                                                                           linux,phandle = <0x1e>;

                                                                           phandle = <0x1e>;

                                                            };

                                                            qspi_clk {

                                                                           #clock-cells = <0x0>;

                                                                           compatible = "altr,socfpga-a10-gate-clk";

                                                                           clocks = <0x3>;

                                                                           clk-gate = <0xc8 0xb>;

                                                                           linux,phandle = <0x23>;

                                                                           phandle = <0x23>;

                                                            };

                                                            nand_clk {

                                                                           #clock-cells = <0x0>;

                                                                           compatible = "altr,socfpga-a10-gate-clk";

                                                                           clocks = <0x17>;

                                                                           clk-gate = <0xc8 0xa>;

                                                                           linux,phandle = <0x1f>;

                                                                           phandle = <0x1f>;

                                                            };

                                                            spi_m_clk {

                                                                           #clock-cells = <0x0>;

                                                                           compatible = "altr,socfpga-a10-gate-clk";

                                                                           clocks = <0x3>;

                                                                           clk-gate = <0xc8 0x9>;

                                                                           linux,phandle = <0x1c>;

                                                                           phandle = <0x1c>;

                                                            };

                                                            usb_clk {

                                                                           #clock-cells = <0x0>;

                                                                           compatible = "altr,socfpga-a10-gate-clk";

                                                                           clocks = <0x17>;

                                                                           clk-gate = <0xc8 0x8>;

                                                                           linux,phandle = <0x26>;

                                                                           phandle = <0x26>;

                                                            };

                                                            s2f_usr1_clk {

                                                                           #clock-cells = <0x0>;

                                                                           compatible = "altr,socfpga-a10-gate-clk";

                                                                           clocks = <0x11>;

                                                                           clk-gate = <0xc8 0x6>;

                                                            };

                                             };

                              };

                              ethernet@ff800000 {

                                             compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";

                                             altr,sysmgr-syscon = <0x18 0x44 0x0>;

                                             reg = <0xff800000 0x2000>;

                                             interrupts = <0x0 0x5c 0x4>;

                                             interrupt-names = "macirq";

                                             mac-address = [00 00 00 00 00 00];

                                             snps,multicast-filter-bins = <0x100>;

                                             snps,perfect-filter-entries = <0x80>;

                                             tx-fifo-depth = <0x1000>;

                                             rx-fifo-depth = <0x4000>;

                                             clocks = <0x17>;

                                             clock-names = "stmmaceth";

                                             resets = <0x19 0x20>;

                                             reset-names = "stmmaceth";

                                             status = "okay";

                                             phy-mode = "rgmii";

                                             phy-addr = <0xffffffff>;

                                             txd0-skew-ps = <0x0>;

                                             txd1-skew-ps = <0x0>;

                                             txd2-skew-ps = <0x0>;

                                             txd3-skew-ps = <0x0>;

                                             rxd0-skew-ps = <0x1a4>;

                                             rxd1-skew-ps = <0x1a4>;

                                             rxd2-skew-ps = <0x1a4>;

                                             rxd3-skew-ps = <0x1a4>;

                                             txen-skew-ps = <0x0>;

                                             txc-skew-ps = <0x744>;

                                             rxdv-skew-ps = <0x1a4>;

                                             rxc-skew-ps = <0x690>;

                                             max-frame-size = <0xed8>;

                                             linux,phandle = <0x21>;

                                             phandle = <0x21>;

                              };

                              ethernet@ff802000 {

                                             compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";

                                             altr,sysmgr-syscon = <0x18 0x48 0x0>;

                                             reg = <0xff802000 0x2000>;

                                             interrupts = <0x0 0x5d 0x4>;

                                             interrupt-names = "macirq";

                                             mac-address = [00 00 00 00 00 00];

                                             snps,multicast-filter-bins = <0x100>;

                                             snps,perfect-filter-entries = <0x80>;

                                             tx-fifo-depth = <0x1000>;

                                             rx-fifo-depth = <0x4000>;

                                             clocks = <0x17>;

                                             clock-names = "stmmaceth";

                                             resets = <0x19 0x21>;

                                             reset-names = "stmmaceth";

                                             status = "disabled";

                              };

                              ethernet@ff804000 {

                                             compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";

                                             altr,sysmgr-syscon = <0x18 0x4c 0x0>;

                                             reg = <0xff804000 0x2000>;

                                             interrupts = <0x0 0x5e 0x4>;

                                             interrupt-names = "macirq";

                                             mac-address = [00 00 00 00 00 00];

                                             snps,multicast-filter-bins = <0x100>;

                                             snps,perfect-filter-entries = <0x80>;

                                             tx-fifo-depth = <0x1000>;

                                             rx-fifo-depth = <0x4000>;

                                             clocks = <0x17>;

                                             clock-names = "stmmaceth";

                                             status = "disabled";

                              };

                              gpio@ffc02900 {

                                             #address-cells = <0x1>;

                                             #size-cells = <0x0>;

                                             compatible = "snps,dw-apb-gpio";

                                             reg = <0xffc02900 0x100>;

                                             status = "disabled";

                                             gpio-controller@0 {

                                                            compatible = "snps,dw-apb-gpio-port";

                                                            gpio-controller;

                                                            #gpio-cells = <0x2>;

                                                            snps,nr-gpios = <0x1d>;

                                                            reg = <0x0>;

                                                            interrupt-controller;

                                                            #interrupt-cells = <0x2>;

                                                            interrupts = <0x0 0x70 0x4>;

                                             };

                              };

                              gpio@ffc02a00 {

                                             #address-cells = <0x1>;

                                             #size-cells = <0x0>;

                                             compatible = "snps,dw-apb-gpio";

                                             reg = <0xffc02a00 0x100>;

                                             status = "okay";

                                             gpio-controller@0 {

                                                            compatible = "snps,dw-apb-gpio-port";

                                                            gpio-controller;

                                                            #gpio-cells = <0x2>;

                                                            snps,nr-gpios = <0x1d>;

                                                            reg = <0x0>;

                                                            interrupt-controller;

                                                            #interrupt-cells = <0x2>;

                                                            interrupts = <0x0 0x71 0x4>;

                                                            linux,phandle = <0x1d>;

                                                            phandle = <0x1d>;

                                             };

                              };

                              gpio@ffc02b00 {

                                             #address-cells = <0x1>;

                                             #size-cells = <0x0>;

                                             compatible = "snps,dw-apb-gpio";

                                             reg = <0xffc02b00 0x100>;

                                             status = "disabled";

                                             gpio-controller@0 {

                                                            compatible = "snps,dw-apb-gpio-port";

                                                            gpio-controller;

                                                            #gpio-cells = <0x2>;

                                                            snps,nr-gpios = <0x1b>;

                                                            reg = <0x0>;

                                                            interrupt-controller;

                                                            #interrupt-cells = <0x2>;

                                                            interrupts = <0x0 0x72 0x4>;

                                             };

                              };

                              fpga-mgr@ffd03000 {

                                             compatible = "altr,socfpga-a10-fpga-mgr";

                                             reg = <0xffd03000 0x100 0xffcfe400 0x20>;

                                             clocks = <0x17>;

                                             resets = <0x19 0x83>;

                                             reset-names = "fpgamgr";

                                             linux,phandle = <0x4>;

                                             phandle = <0x4>;

                              };

                              i2c@ffc02200 {

                                             #address-cells = <0x1>;

                                             #size-cells = <0x0>;

                                             compatible = "snps,designware-i2c";

                                             reg = <0xffc02200 0x100>;

                                             interrupts = <0x0 0x69 0x4>;

                                             clocks = <0x1a>;

                                             status = "disabled";

                              };

                              i2c@ffc02300 {

                                             #address-cells = <0x1>;

                                             #size-cells = <0x0>;

                                             compatible = "snps,designware-i2c";

                                             reg = <0xffc02300 0x100>;

                                             interrupts = <0x0 0x6a 0x4>;

                                             clocks = <0x1a>;

                                             status = "okay";

                                             clock-frequency = <0x186a0>;

                                             i2c-sda-falling-time-ns = <0x1770>;

                                             i2c-scl-falling-time-ns = <0x1770>;

                                             lcd@28 {

                                                            compatible = "newhaven,nhd-0216k3z-nsw-bbw";

                                                            reg = <0x28>;

                                                            height = <0x2>;

                                                            width = <0x10>;

                                                            brightness = <0x8>;

                                             };

                                             eeprom@51 {

                                                            compatible = "atmel,24c32";

                                                            reg = <0x51>;

                                                            pagesize = <0x20>;

                                             };

                                             rtc@68 {

                                                            compatible = "dallas,ds1339";

                                                            reg = <0x68>;

                                             };

                                             max@4c {

                                                            compatible = "max1619";

                                                            reg = <0x4c>;

                                             };

                                             ltc@5c {

                                                            compatible = "ltc2977";

                                                            reg = <0x5c>;

                                             };

                              };

                              i2c@ffc02400 {

                                             #address-cells = <0x1>;

                                             #size-cells = <0x0>;

                                             compatible = "snps,designware-i2c";

                                             reg = <0xffc02400 0x100>;

                                             interrupts = <0x0 0x6b 0x4>;

                                             clocks = <0x1a>;

                                             status = "disabled";

                              };

                              i2c@ffc02500 {

                                             #address-cells = <0x1>;

                                             #size-cells = <0x0>;

                                             compatible = "snps,designware-i2c";

                                             reg = <0xffc02500 0x100>;

                                             interrupts = <0x0 0x6c 0x4>;

                                             clocks = <0x1a>;

                                             status = "disabled";

                              };

                              i2c@ffc02600 {

                                             #address-cells = <0x1>;

                                             #size-cells = <0x0>;

                                             compatible = "snps,designware-i2c";

                                             reg = <0xffc02600 0x100>;

                                             interrupts = <0x0 0x6d 0x4>;

                                             clocks = <0x1a>;

                                             status = "disabled";

                              };

                              spi@ffda5000 {

                                             compatible = "snps,dw-apb-ssi";

                                             #address-cells = <0x1>;

                                             #size-cells = <0x0>;

                                             reg = <0xffda5000 0x100>;

                                             interrupts = <0x0 0x66 0x4>;

                                             num-chipselect = <0x4>;

                                             bus-num = <0x0>;

                                             tx-dma-channel = <0x1b 0x10>;

                                             rx-dma-channel = <0x1b 0x11>;

                                             clocks = <0x1c>;

                                             status = "okay";

                                             resource-manager@0 {

                                                            compatible = "altr,a10sr";

                                                            reg = <0x0>;

                                                            spi-max-frequency = <0x186a0>;

                                                            interrupt-parent = <0x1d>;

                                                            interrupts = <0x5 0x8>;

                                                            interrupt-controller;

                                                            #interrupt-cells = <0x2>;

                                                            gpio-controller {

                                                                           compatible = "altr,a10sr-gpio";

                                                                           gpio-controller;

                                                                           #gpio-cells = <0x2>;

                                                                           linux,phandle = <0x39>;

                                                                           phandle = <0x39>;

                                                            };

                                                            ps_alarm {

                                                                           compatible = "altr,a10sr-hwmon";

                                                            };

                                             };

                              };

                              sdr@ffc25000 {

                                             compatible = "altr,sdr-ctl", "syscon";

                                             reg = <0xffcfb100 0x80>;

                                             linux,phandle = <0x20>;

                                             phandle = <0x20>;

                              };

                              l2-cache@fffff000 {

                                             compatible = "arm,pl310-cache";

                                             reg = <0xfffff000 0x1000>;

                                             interrupts = <0x0 0x12 0x4>;

                                             cache-unified;

                                             cache-level = <0x2>;

                                             prefetch-data = <0x1>;

                                             prefetch-instr = <0x1>;

                                             arm,shared-override;

                                             linux,phandle = <0x1>;

                                             phandle = <0x1>;

                              };

                              dwmmc0@ff808000 {

                                             #address-cells = <0x1>;

                                             #size-cells = <0x0>;

                                             compatible = "altr,socfpga-dw-mshc";

                                             reg = <0xff808000 0x1000>;

                                             interrupts = <0x0 0x62 0x4>;

                                             fifo-depth = <0x400>;

                                             clocks = <0x17 0x1e>;

                                             clock-names = "biu", "ciu";

                                             status = "okay";

                                             num-slots = <0x1>;

                                             cap-sd-highspeed;

                                             broken-cd;

                                             bus-width = <0x4>;

                                             altr,dw-mshc-ciu-div = <0x3>;

                                             altr,dw-mshc-sdr-timing = <0x0 0x3>;

                              };

                              nand@ffb90000 {

                                             #address-cells = <0x1>;

                                             #size-cells = <0x1>;

                                             compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";

                                             reg = <0xffb90000 0x72000 0xffb80000 0x10000>;

                                             reg-names = "nand_data", "denali_reg";

                                             interrupts = <0x0 0x63 0x4>;

                                             dma-mask = <0xffffffff>;

                                             clocks = <0x1f>;

                                             status = "disabled";

                              };

                              sram@ffe00000 {

                                             compatible = "mmio-sram";

                                             reg = <0xffe00000 0x40000>;

                              };

                              eccmgr@ffd06000 {

                                             compatible = "altr,socfpga-a10-ecc-manager";

                                             altr,sysmgr-syscon = <0x18>;

                                             #address-cells = <0x1>;

                                             #size-cells = <0x1>;

                                             interrupts = <0x0 0x2 0x4 0x0 0x0 0x4>;

                                             interrupt-controller;

                                             #interrupt-cells = <0x2>;

                                             ranges;

                                             sdramedac {

                                                            compatible = "altr,sdram-edac-a10";

                                                            altr,sdr-syscon = <0x20>;

                                                            interrupts = <0x11 0x4 0x31 0x4>;

                                             };

                                             l2-ecc@ffd06010 {

                                                            compatible = "altr,socfpga-a10-l2-ecc";

                                                            reg = <0xffd06010 0x4>;

                                                            interrupts = <0x0 0x4 0x20 0x4>;

                                             };

                                             ocram-ecc@ff8c3000 {

                                                            compatible = "altr,socfpga-a10-ocram-ecc";

                                                            reg = <0xff8c3000 0x400>;

                                                            interrupts = <0x1 0x4 0x21 0x4>;

                                             };

                                             emac0-rx-ecc@ff8c0800 {

                                                            compatible = "altr,socfpga-eth-mac-ecc";

                                                            reg = <0xff8c0800 0x400>;

                                                            altr,ecc-parent = <0x21>;

                                                            interrupts = <0x4 0x4 0x24 0x4>;

                                             };

                                             emac0-tx-ecc@ff8c0c00 {

                                                            compatible = "altr,socfpga-eth-mac-ecc";

                                                            reg = <0xff8c0c00 0x400>;

                                                            altr,ecc-parent = <0x21>;

                                                            interrupts = <0x5 0x4 0x25 0x4>;

                                             };

                                             dma-ecc@ff8c8000 {

                                                            compatible = "altr,socfpga-dma-ecc";

                                                            reg = <0xff8c8000 0x400>;

                                                            altr,ecc-parent = <0x1b>;

                                                            interrupts = <0xa 0x4 0x2a 0x4>;

                                             };

                                             usb0-ecc@ff8c8800 {

                                                            compatible = "altr,socfpga-usb-ecc";

                                                            reg = <0xff8c8800 0x400>;

                                                            altr,ecc-parent = <0x22>;

                                                            interrupts = <0x2 0x4 0x22 0x4>;

                                             };

                              };

                              spi@ff809000 {

                                             compatible = "cdns,qspi-nor";

                                             #address-cells = <0x1>;

                                             #size-cells = <0x0>;

                                             reg = <0xff809000 0x100 0xffa00000 0x100000>;

                                             interrupts = <0x0 0x64 0x4>;

                                             cdns,fifo-depth = <0x80>;

                                             cdns,fifo-width = <0x4>;

                                             cdns,trigger-address = <0x0>;

                                             clocks = <0x23>;

                                             status = "disabled";

                              };

                              rstmgr@ffd05000 {

                                             #reset-cells = <0x1>;

                                             compatible = "altr,rst-mgr";

                                             reg = <0xffd05000 0x100>;

                                             altr,modrst-offset = <0x20>;

                                             linux,phandle = <0x19>;

                                             phandle = <0x19>;

                              };

                              snoop-control-unit@ffffc000 {

                                             compatible = "arm,cortex-a9-scu";

                                             reg = <0xffffc000 0x100>;

                              };

                              sysmgr@ffd06000 {

                                             compatible = "altr,sys-mgr", "syscon";

                                             reg = <0xffd06000 0x300>;

                                             cpu1-start-addr = <0xffd06230>;

                                             linux,phandle = <0x18>;

                                             phandle = <0x18>;

                              };

                              timer@ffffc600 {

                                             compatible = "arm,cortex-a9-twd-timer";

                                             reg = <0xffffc600 0x100>;

                                             interrupts = <0x1 0xd 0xf04>;

                                             clocks = <0x24>;

                              };

                              timer0@ffc02700 {

                                             compatible = "snps,dw-apb-timer";

                                             interrupts = <0x0 0x73 0x4>;

                                             reg = <0xffc02700 0x100>;

                                             clocks = <0x1a>;

                                             clock-names = "timer";

                              };

                              timer1@ffc02800 {

                                             compatible = "snps,dw-apb-timer";

                                             interrupts = <0x0 0x74 0x4>;

                                             reg = <0xffc02800 0x100>;

                                             clocks = <0x1a>;

                                             clock-names = "timer";

                              };

                              timer2@ffd00000 {

                                             compatible = "snps,dw-apb-timer";

                                             interrupts = <0x0 0x75 0x4>;

                                             reg = <0xffd00000 0x100>;

                                             clocks = <0x25>;

                                             clock-names = "timer";

                              };

                              timer3@ffd00100 {

                                             compatible = "snps,dw-apb-timer";

                                             interrupts = <0x0 0x76 0x4>;

                                             reg = <0xffd01000 0x100>;

                                             clocks = <0x25>;

                                             clock-names = "timer";

                              };

                              serial0@ffc02000 {

                                             compatible = "snps,dw-apb-uart";

                                             reg = <0xffc02000 0x100>;

                                             interrupts = <0x0 0x6e 0x4>;

                                             reg-shift = <0x2>;

                                             reg-io-width = <0x4>;

                                             clocks = <0x1a>;

                                             status = "disabled";

                              };

                              serial1@ffc02100 {

                                             compatible = "snps,dw-apb-uart";

                                             reg = <0xffc02100 0x100>;

                                             interrupts = <0x0 0x6f 0x4>;

                                             reg-shift = <0x2>;

                                             reg-io-width = <0x4>;

                                             clocks = <0x1a>;

                                             status = "okay";

                              };

                              usbphy@0 {

                                             #phy-cells = <0x0>;

                                             compatible = "usb-nop-xceiv";

                                             status = "okay";

                                             linux,phandle = <0x27>;

                                             phandle = <0x27>;

                              };

                              usb@ffb00000 {

                                             compatible = "snps,dwc2";

                                             reg = <0xffb00000 0xffff>;

                                             interrupts = <0x0 0x5f 0x4>;

                                             clocks = <0x26>;

                                             clock-names = "otg";

                                             resets = <0x19 0x23>;

                                             reset-names = "dwc2";

                                             phys = <0x27>;

                                             phy-names = "usb2-phy";

                                             status = "okay";

                                             linux,phandle = <0x22>;

                                             phandle = <0x22>;

                              };

                              usb@ffb40000 {

                                             compatible = "snps,dwc2";

                                             reg = <0xffb40000 0xffff>;

                                             interrupts = <0x0 0x60 0x4>;

                                             clocks = <0x26>;

                                             clock-names = "otg";

                                             resets = <0x19 0x24>;

                                             reset-names = "dwc2";

                                             phys = <0x27>;

                                             phy-names = "usb2-phy";

                                             status = "disabled";

                              };

                              watchdog@ffd00200 {

                                             compatible = "snps,dw-wdt";

                                             reg = <0xffd00200 0x100>;

                                             interrupts = <0x0 0x77 0x4>;

                                             clocks = <0x25>;

                                             status = "okay";

                              };

                              watchdog@ffd00300 {

                                             compatible = "snps,dw-wdt";

                                             reg = <0xffd00300 0x100>;

                                             interrupts = <0x0 0x78 0x4>;

                                             clocks = <0x25>;

                                             status = "disabled";

                              };

                              bridge@ff200000 {

                                             compatible = "simple-bus";

                                             reg = <0xff200000 0x200000>;

                                             #address-cells = <0x1>;

                                             #size-cells = <0x1>;

                                             ranges = <0x0 0xff200000 0x200000>;

                                             gpio@20 {

                                                            compatible = "altr,pio-1.0";

                                                            reg = <0x20 0x10>;

                                                            altr,gpio-bank-width = <0x20>;

                                                            resetvalue = <0x0>;

                                                            #gpio-cells = <0x2>;

                                                            gpio-controller;

                                                            linux,phandle = <0x28>;

                                                            phandle = <0x28>;

                                             };

                                             spi@40 {

                                                            compatible = "altr,spi-1.0";

                                                            reg = <0x40 0x20>;

                                                            interrupt-parent = <0x2>;

                                                            interrupts = <0x0 0x1a 0x4>;

                                                            #address-cells = <0x1>;

                                                            #size-cells = <0x0>;

                                                            ad9528-1@0 {

                                                                           #address-cells = <0x1>;

                                                                           #size-cells = <0x0>;

                                                                           #clock-cells = <0x1>;

                                                                           compatible = "ad9528";

                                                                           spi-max-frequency = <0x989680>;

                                                                           reg = <0x0>;

                                                                           clock-output-names = "ad9528-1_out0", "ad9528-1_out1", "ad9528-1_out2", "ad9528-1_out3", "ad9528-1_out4", "ad9528-1_out5", "ad9528-1_out6", "ad9528-1_out7", "ad9528-1_out8", "ad9528-1_out9", "ad9528-1_out10", "ad9528-1_out11", "ad9528-1_out12", "ad9528-1_out13";

                                                                           adi,vcxo-freq = <0x4c4b400>;

                                                                           adi,refa-enable;

                                                                           adi,refa-diff-rcv-enable;

                                                                           adi,refa-r-div = <0x1>;

                                                                           adi,osc-in-cmos-neg-inp-enable;

                                                                           adi,pll1-feedback-div = <0x4>;

                                                                           adi,pll1-charge-pump-current-nA = <0x1388>;

                                                                           adi,pll2-vco-div-m1 = <0x4>;

                                                                           adi,pll2-n2-div = <0xc>;

                                                                           adi,pll2-r1-div = <0x1>;

                                                                           adi,pll2-charge-pump-current-nA = <0xc4888>;

                                                                           adi,sysref-src = <0x2>;

                                                                           adi,sysref-pattern-mode = <0x1>;

                                                                           adi,sysref-k-div = <0x200>;

                                                                           adi,sysref-request-enable;

                                                                           adi,sysref-nshot-mode = <0x3>;

                                                                           adi,sysref-request-trigger-mode = <0x0>;

                                                                           adi,rpole2 = <0x0>;

                                                                           adi,rzero = <0x7>;

                                                                           adi,cpole1 = <0x2>;

                                                                           adi,status-mon-pin0-function-select = <0x1>;

                                                                           adi,status-mon-pin1-function-select = <0x7>;

                                                                           reset-gpios = <0x28 0x1b 0x0>;

                                                                           linux,phandle = <0x2c>;

                                                                           phandle = <0x2c>;

                                                                           channel@13 {

                                                                                          reg = <0xd>;

                                                                                          adi,extended-name = "DEV_CLK";

                                                                                          adi,driver-mode = <0x0>;

                                                                                          adi,divider-phase = <0x0>;

                                                                                          adi,channel-divider = <0x3>;

                                                                                          adi,signal-source = <0x0>;

                                                                           };

                                                                           channel@1 {

                                                                                          reg = <0x1>;

                                                                                          adi,extended-name = "FMC_CLK";

                                                                                          adi,driver-mode = <0x0>;

                                                                                          adi,divider-phase = <0x0>;

                                                                                          adi,channel-divider = <0x3>;

                                                                                          adi,signal-source = <0x0>;

                                                                           };

                                                                           channel@12 {

                                                                                          reg = <0xc>;

                                                                                          adi,extended-name = "DEV_SYSREF";

                                                                                          adi,driver-mode = <0x0>;

                                                                                          adi,divider-phase = <0x0>;

                                                                                          adi,channel-divider = <0x3>;

                                                                                          adi,signal-source = <0x2>;

                                                                           };

                                                                           channel@3 {

                                                                                          reg = <0x3>;

                                                                                          adi,extended-name = "FMC_SYSREF";

                                                                                          adi,driver-mode = <0x0>;

                                                                                          adi,divider-phase = <0x0>;

                                                                                          adi,channel-divider = <0x3>;

                                                                                          adi,signal-source = <0x2>;

                                                                           };

                                                            };

                                                            ad9371-phy@1 {

                                                                           #address-cells = <0x1>;

                                                                           #size-cells = <0x0>;

                                                                           #clock-cells = <0x1>;

                                                                           compatible = "ad9371";

                                                                           reg = <0x1>;

                                                                           spi-max-frequency = <0x17d7840>;

                                                                           clocks = <0x29 0x2a 0x2b 0x2c 0xd 0x2c 0x1>;

                                                                           clock-names = "jesd_rx_clk", "jesd_tx_clk", "jesd_rx_os_clk", "dev_clk", "fmc_clk";

                                                                           clock-output-names = "rx_sampl_clk", "rx_os_sampl_clk", "tx_sampl_clk";

                                                                           adi,clocks-clk-pll-vco-freq_khz = <9600000>;

                                                                           adi,clocks-device-clock_khz = <320000>;

                                                                           adi,clocks-clk-pll-hs-div = <0x4>;

                                                                           adi,clocks-clk-pll-vco-div = <0x3>;

                                                                           adi,jesd204-obs-framer-over-sample = <0x0>;

                                                                           adi,rx-profile-adc-div = <0x1>;

                                                                           adi,rx-profile-en-high-rej-dec5 = <0x1>;

                                                                           adi,rx-profile-iq-rate_khz = <0x13880>;

                                                                           adi,rx-profile-rf-bandwidth_hz = <0x2625a00>;

                                                                           adi,rx-profile-rhb1-decimation = <0x1>;

                                                                           adi,rx-profile-rx-bbf-3db-corner_khz = <0x9c40>;

                                                                           adi,rx-profile-rx-dec5-decimation = <0x5>;

                                                                           adi,rx-profile-rx-fir-decimation = <0x2>;

                                                                           adi,rx-profile-rx-fir-gain_db = <(-6)>;

                                                                           adi,rx-profile-rx-fir-num-fir-coefs = <48>;

                                                                           adi,rx-profile-rx-fir-coefs = <(1) (7) (3) (-20) (-38) (10) (107) (100) (-122) (-334) (-113) (506) (718) (-166) (-1391) (-1095) (1231) (3033) (981) (-4224) (-6482) (219) (14325) (26107) (26107) (14325) (219) (-6482) (-4224) (981) (3033) (1231) (-1095) (-1391) (-166) (718) (506) (-113) (-334) (-122) (100) (107) (10) (-38) (-20) (3) (7) (1)>;

                                                                           adi,rx-profile-custom-adc-profile = <900 559 201 98 1280 199 1522 98 860 25 529 37 48 26 15 196>;

                                                                           adi,obs-profile-adc-div = <0x1>;

                                                                           adi,obs-profile-en-high-rej-dec5 = <0x1>;

                                                                           adi,obs-profile-iq-rate_khz = <0x13880>;

                                                                           adi,obs-profile-rf-bandwidth_hz = <0x2625a00>;

                                                                           adi,obs-profile-rhb1-decimation = <0x1>;

                                                                           adi,obs-profile-rx-bbf-3db-corner_khz = <0x4e20>;

                                                                           adi,obs-profile-rx-dec5-decimation = <0x5>;

                                                                           adi,obs-profile-rx-fir-decimation = <0x2>;

                                                                           adi,obs-profile-rx-fir-gain_db = <(-6)>;

                                                                           adi,obs-profile-rx-fir-num-fir-coefs = <48>;

                                                                           adi,obs-profile-rx-fir-coefs = <(-1) (10) (10) (-22) (-60) (-6) (143) (171) (-129) (-485) (-245) (660) (1099) (-74) (-1954) (-1784) (1506) (4443) (1920) (-5737) (-10210) (-2631) (15550) (31189) (31189) (15550) (-2631) (-10210) (-5737) (1920) (4443) (1506) (-1784) (-1954) (-74) (1099) (660) (-245) (-485) (-129) (171) (143) (-6) (-60) (-22) (10) (10) (-1)>;

                                                                           adi,obs-profile-custom-adc-profile = <900 559 201 98 1280 199 1522 98 860 25 529 37 48 26 15 196>;

                                                                           adi,obs-settings-custom-loopback-adc-profile = <922 550 201 98 1280 112 1505 53 864 14 533 40 48 26 15 197>;

                                                                           adi,tx-profile-dac-div = <0x1>;

                                                                           adi,tx-profile-iq-rate_khz = <0x13880>;

                                                                           adi,tx-profile-primary-sig-bandwidth_hz = <0x1312d00>;

                                                                           adi,tx-profile-rf-bandwidth_hz = <0x2625a00>;

                                                                           adi,tx-profile-thb1-interpolation = <0x2>;

                                                                           adi,tx-profile-thb2-interpolation = <0x2>;

                                                                           adi,tx-profile-tx-bbf-3db-corner_khz = <0x4e20>;

                                                                           adi,tx-profile-tx-dac-3db-corner_khz = <0x16760>;

                                                                           adi,tx-profile-tx-fir-interpolation = <0x1>;

                                                                           adi,tx-profile-tx-input-hb-interpolation = <0x1>;

                                                                           adi,tx-profile-tx-fir-gain_db = <6>;

                                                                           adi,tx-profile-tx-fir-num-fir-coefs = <16>;

                                                                           adi,tx-profile-tx-fir-coefs = <26 (-292) (-75) 333 339 (-659) (-2192) 21034 (-2192) (-659) 339 333 (-75) (-292) 26 0>;

                                                                           adi,sniffer-profile-adc-div = <0x1>;

                                                                           adi,sniffer-profile-en-high-rej-dec5 = <0x1>;

                                                                           adi,sniffer-profile-iq-rate_khz = <0x9c40>;

                                                                           adi,sniffer-profile-rf-bandwidth_hz = <0x1312d00>;

                                                                           adi,sniffer-profile-rhb1-decimation = <0x2>;

                                                                           adi,sniffer-profile-rx-bbf-3db-corner_khz = <0x4e20>;

                                                                           adi,sniffer-profile-rx-dec5-decimation = <0x5>;

                                                                           adi,sniffer-profile-rx-fir-decimation = <0x2>;

                                                                           adi,sniffer-profile-rx-fir-gain_db = <(-6)>;

                                                                           adi,sniffer-profile-rx-fir-num-fir-coefs = <72>;

                                                                           adi,sniffer-profile-rx-fir-coefs = <(-9) (12) (18) (17) (-17) (-49) (-45) (21) (99) (105) (-11) (-171) (-215) (-36) (258) (390) (149) (-343) (-648) (-371) (394) (1003) (763) (-357) (-1476) (-1425) (138) (2113) (2589) (489) (-3082) (-5079) (-2537) (4990) (14500) (21095) (21095) (14500) (4990) (-2537) (-5079) (-3082) (489) (2589) (2113) (138) (-1425) (-1476) (-357) (763) (1003) (394) (-371) (-648) (-343) (149) (390) (258) (-36) (-215) (-171) (-11) (105) (99) (21) (-45) (-49) (-17) (17) (18) (12) (-9)>;

                                                                           adi,sniffer-profile-custom-adc-profile = <922 550 201 98 1280 112 1505 53 864 14 533 40 48 26 15 197>;

                                                                           reset-gpios = <0x28 0x14 0x0>;

                                                                           test-gpios = <0x28 0x15 0x0>;

                                                                           sysref_req-gpios = <0x28 0x1a 0x0>;

                                                                           rx2_enable-gpios = <0x28 0x16 0x0>;

                                                                           rx1_enable-gpios = <0x28 0x17 0x0>;

                                                                           tx2_enable-gpios = <0x28 0x18 0x0>;

                                                                           tx1_enable-gpios = <0x28 0x19 0x0>;

                                                                           linux,phandle = <0x36>;

                                                                           phandle = <0x36>;

                                                            };

                                             };

                                             axi-jesd204-tx@20000 {

                                                            compatible = "adi,axi-jesd204-tx-1.0";

                                                            reg = <0x20000 0x4000>;

                                                            interrupt-parent = <0x2>;

                                                            interrupts = <0x0 0x1c 0x0>;

                                                            clocks = <0x2d 0x2e 0x2f>;

                                                            clock-names = "s_axi_aclk", "device_clk", "lane_clk";

                                                            adi,octets-per-frame = <0x2>;

                                                            adi,frames-per-multiframe = <0x20>;

                                                            adi,converter-resolution = <0xe>;

                                                            adi,bits-per-sample = <0x10>;

                                                            adi,converters-per-device = <0x4>;

                                                            adi,control-bits-per-sample = <0x2>;

                                                            #clock-cells = <0x0>;

                                                            clock-output-names = "jesd_tx_lane_clk";

                                                            linux,phandle = <0x2a>;

                                                            phandle = <0x2a>;

                                             };

                                             axi-jesd204-rx@30000 {

                                                            compatible = "adi,axi-jesd204-rx-1.0";

                                                            reg = <0x30000 0x4000>;

                                                            interrupt-parent = <0x2>;

                                                            interrupts = <0x0 0x1b 0x0>;

                                                            clocks = <0x2d 0x30 0x31>;

                                                            clock-names = "s_axi_aclk", "device_clk", "lane_clk";

                                                            adi,octets-per-frame = <0x4>;

                                                            adi,frames-per-multiframe = <0x20>;

                                                            adi,converter-resolution = <0x10>;

                                                            adi,bits-per-sample = <0x10>;

                                                            adi,converters-per-device = <0x4>;

                                                            #clock-cells = <0x0>;

                                                            clock-output-names = "jesd_rx_lane_clk";

                                                            linux,phandle = <0x29>;

                                                            phandle = <0x29>;

                                             };

                                             axi-jesd204-rx@40000 {

                                                            compatible = "adi,axi-jesd204-rx-1.0";

                                                            reg = <0x40000 0x4000>;

                                                            interrupt-parent = <0x2>;

                                                            interrupts = <0x0 0x1d 0x0>;

                                                            clocks = <0x2d 0x32 0x33>;

                                                            clock-names = "s_axi_aclk", "device_clk", "lane_clk";

                                                            adi,octets-per-frame = <0x2>;

                                                            adi,frames-per-multiframe = <0x20>;

                                                            adi,converter-resolution = <0x10>;

                                                            adi,bits-per-sample = <0x10>;

                                                            adi,converters-per-device = <0x4>;

                                                            #clock-cells = <0x0>;

                                                            clock-output-names = "jesd_rx_os_lane_clk";

                                                            linux,phandle = <0x2b>;

                                                            phandle = <0x2b>;

                                             };

                                             axi-ad9371-tx-xcvr@24000 {

                                                            compatible = "adi,altera-adxcvr-1.00.a";

                                                            reg = <0x24000 0x1000 0x26000 0x1000 0x28000 0x1000 0x29000 0x1000 0x2a000 0x1000 0x2b000 0x1000>;

                                                            reg-names = "adxcvr", "atx-pll", "adxcfg-0", "adxcfg-1", "adxcfg-2", "adxcfg-3";

                                                            clocks = <0x2c 0x1 0x2e>;

                                                            clock-names = "ref", "link";

                                                            #clock-cells = <0x0>;

                                                            clock-output-names = "jesd204_tx_lane_clock";

                                                            linux,phandle = <0x2f>;

                                                            phandle = <0x2f>;

                                             };

                                             axi-ad9371-rx-xcvr@34000 {

                                                            compatible = "adi,altera-adxcvr-1.00.a";

                                                            reg = <0x34000 0x1000 0x38000 0x1000 0x39000 0x1000>;

                                                            reg-names = "adxcvr", "adxcfg-0", "adxcfg-1";

                                                            clocks = <0x2c 0x1 0x30>;

                                                            clock-names = "ref", "link";

                                                            #clock-cells = <0x0>;

                                                            clock-output-names = "jesd204_rx_lane_clock";

                                                            linux,phandle = <0x31>;

                                                            phandle = <0x31>;

                                             };

                                             axi-ad9371-rx-os-xcvr@44000 {

                                                            compatible = "adi,altera-adxcvr-1.00.a";

                                                            reg = <0x44000 0x1000 0x48000 0x1000 0x49000 0x1000>;

                                                            reg-names = "adxcvr", "adxcfg-0", "adxcfg-1";

                                                            clocks = <0x2c 0x1 0x32>;

                                                            clock-names = "ref", "link";

                                                            #clock-cells = <0x0>;

                                                            clock-output-names = "jesd204_rx_os_lane_clock";

                                                            linux,phandle = <0x33>;

                                                            phandle = <0x33>;

                                             };

                                             axi-ad9371-tx-dma@2c000 {

                                                            compatible = "adi,axi-dmac-1.00.a";

                                                            reg = <0x2c000 0x4000>;

                                                            interrupt-parent = <0x2>;

                                                            interrupts = <0x0 0x1e 0x4>;

                                                            #dma-cells = <0x1>;

                                                            clocks = <0x34>;

                                                            linux,phandle = <0x37>;

                                                            phandle = <0x37>;

                                                            dma-channel {

                                                                           adi,source-bus-width = <0x80>;

                                                                           adi,destination-bus-width = <0x80>;

                                                                           adi,type = <0x1>;

                                                            };

                                             };

                                             axi-ad9371-rx-dma@3c000 {

                                                            compatible = "adi,axi-dmac-1.00.a";

                                                            reg = <0x3c000 0x4000>;

                                                            interrupt-parent = <0x2>;

                                                            interrupts = <0x0 0x1f 0x4>;

                                                            #dma-cells = <0x1>;

                                                            clocks = <0x34>;

                                                            linux,phandle = <0x35>;

                                                            phandle = <0x35>;

                                                            dma-channel {

                                                                           adi,source-bus-width = <0x40>;

                                                                           adi,destination-bus-width = <0x80>;

                                                                           adi,type = <0x0>;

                                                            };

                                             };

                                             axi-ad9371-rx-os-dma@4c000 {

                                                            compatible = "adi,axi-dmac-1.00.a";

                                                            reg = <0x4c000 0x4000>;

                                                            interrupt-parent = <0x2>;

                                                            interrupts = <0x0 0x20 0x4>;

                                                            #dma-cells = <0x1>;

                                                            clocks = <0x34>;

                                                            linux,phandle = <0x38>;

                                                            phandle = <0x38>;

                                                            dma-channel {

                                                                           adi,source-bus-width = <0x40>;

                                                                           adi,destination-bus-width = <0x80>;

                                                                           adi,type = <0x0>;

                                                            };

                                             };

                                             axi-ad9371-rx-hpc@50000 {

                                                            compatible = "adi,axi-ad9371-rx-1.0";

                                                            reg = <0x50000 0x8000>;

                                                            dmas = <0x35 0x0>;

                                                            dma-names = "rx";

                                                            spibus-connected = <0x36>;

                                             };

                                             axi-ad9371-tx-hpc@54000 {

                                                            compatible = "adi,axi-ad9371-tx-1.0";

                                                            reg = <0x54000 0x4000>;

                                                            dmas = <0x37 0x0>;

                                                            dma-names = "tx";

                                                            clocks = <0x36 0x2>;

                                                            clock-names = "sampl_clk";

                                                            spibus-connected = <0x36>;

                                                            adi,axi-pl-fifo-enable;

                                                            plddrbypass-gpios = <0x28 0x1c 0x0>;

                                             };

                                             axi-ad9371-rx-obs-hpc@58000 {

                                                            compatible = "adi,axi-ad9371-obs-1.0";

                                                            reg = <0x58000 0x1000>;

                                                            dmas = <0x38 0x0>;

                                                            dma-names = "rx";

                                                            clocks = <0x36 0x1>;

                                                            clock-names = "sampl_clk";

                                             };

                                             altera-a10-fpll@25000 {

                                                            compatible = "altr,a10-fpll";

                                                            reg = <0x25000 0x1000>;

                                                            clocks = <0x2c 0x1>;

                                                            #clock-cells = <0x0>;

                                                            clock-output-names = "jesd204_tx_link_clock";

                                                            linux,phandle = <0x2e>;

                                                            phandle = <0x2e>;

                                             };

                                             altera-a10-fpll@35000 {

                                                            compatible = "altr,a10-fpll";

                                                            reg = <0x35000 0x1000>;

                                                            clocks = <0x2c 0x1>;

                                                            #clock-cells = <0x0>;

                                                            clock-output-names = "jesd204_rx_link_clock";

                                                            linux,phandle = <0x30>;

                                                            phandle = <0x30>;

                                             };

                                             altera-a10-fpll@45000 {

                                                            compatible = "altr,a10-fpll";

                                                            reg = <0x45000 0x1000>;

                                                            clocks = <0x2c 0x1>;

                                                            #clock-cells = <0x0>;

                                                            clock-output-names = "jesd204_rx_os_link_clock";

                                                            linux,phandle = <0x32>;

                                                            phandle = <0x32>;

                                             };

                              };

               };

               a10leds {

                              compatible = "gpio-leds";

                              a10sr_led0 {

                                             label = "a10sr-led0";

                                             gpios = <0x39 0x0 0x1>;

                              };

                              a10sr_led1 {

                                             label = "a10sr-led1";

                                             gpios = <0x39 0x1 0x1>;

                              };

                              a10sr_led2 {

                                             label = "a10sr-led2";

                                             gpios = <0x39 0x2 0x1>;

                              };

                              a10sr_led3 {

                                             label = "a10sr-led3";

                                             gpios = <0x39 0x3 0x1>;

                              };

               };

               clocks {

                              sys_clk {

                                             #clock-cells = <0x0>;

                                             compatible = "fixed-clock";

                                             clock-frequency = <0x5f5e100>;

                                             clock-output-names = "system_clock";

                                             linux,phandle = <0x2d>;

                                             phandle = <0x2d>;

                              };

                              dma_clk {

                                             #clock-cells = <0x0>;

                                             compatible = "fixed-clock";

                                             clock-frequency = <0xee6b280>;

                                             clock-output-names = "dma_clk";

                                             linux,phandle = <0x34>;

                                             phandle = <0x34>;

                              };

                              clock@0 {

                                             #clock-cells = <0x0>;

                                             compatible = "fixed-clock";

                                             clock-frequency = <0x7a1200>;

                                             clock-output-names = "ad9371_ext_refclk";

                              };

               };

};

My sampling rate is 80Msps, but device clock is 320MHz (80MHz *4). It is because JESD links do not “like” sampling rate the same as device clock and work much better at device clock multiple of sampling rate.

(but calibration is failing at 80MHz device clk as well)

Tx QEC can fail if matching is not correct or if you are using a very large Tx attenuation setting. Since you are using Eval board matching should be Ok.

As Michael mentioned , you should use the profile wizard to create custom profile which matches your sampling rate requirement. 

I generate a profile using Filter Wiz. For 80Msps (see setting on .jpg image)

If I load this profile, I get following error (which is correct, this settings are not supported by AD9371 PLL).

socfpga> [  416.515536] ERROR: 64: CLKPLL VCO frequency exceeded max(9.216Ghz) in VCO divider /1.5 case ()
[  416.524130] ERROR: 64: CLKPLL VCO frequency exceeded max(9.216Ghz) in VCO divider /1.5 case ()
[  416.532721] ad9371 spi32766.1: CLKPLL VCO frequency exceeded max(9.216Ghz) in VCO divider /1.5 case ()
[  416.532721]  (64)
[  417.865480] ERROR: 64: CLKPLL VCO frequency exceeded max(9.216Ghz) in VCO divider /1.5 case ()
[  417.874067] ERROR: 64: CLKPLL VCO frequency exceeded max(9.216Ghz) in VCO divider /1.5 case ()
[  417.882658] ad9371 spi32766.1: CLKPLL VCO frequency exceeded max(9.216Ghz) in VCO divider /1.5 case ()
[  417.882658]  (64)
[  417.894342] ------------[ cut here ]------------
[  417.898954] WARNING: CPU: 0 PID: 911 at drivers/clk/clk.c:622 clk_core_disable+0xb0/0x194
[  417.907091] Modules linked in: mwipcore mwipcore_iio_streaming mwipcore_iio_mm mwipcore_dma_streaming mathworks_ip_common
[  417.918070] CPU: 0 PID: 911 Comm: cat Not tainted 4.9.0 #2
[  417.923528] Hardware name: Altera SOCFPGA Arria10
[  417.928226] [<c01110e0>] (unwind_backtrace) from [<c010caec>] (show_stack+0x20/0x24)
[  417.935940] [<c010caec>] (show_stack) from [<c03e839c>] (dump_stack+0x98/0xac)
[  417.943133] [<c03e839c>] (dump_stack) from [<c011fe50>] (__warn+0xf8/0x110)
[  417.950066] [<c011fe50>] (__warn) from [<c011ff38>] (warn_slowpath_null+0x30/0x38)
[  417.957603] [<c011ff38>] (warn_slowpath_null) from [<c0429bec>] (clk_core_disable+0xb0/0x194)
[  417.966092] [<c0429bec>] (clk_core_disable) from [<c0429f94>] (clk_core_disable_lock+0x28/0x34)
[  417.974751] [<c0429f94>] (clk_core_disable_lock) from [<c0429fcc>] (clk_disable+0x2c/0x30)
[  417.982981] [<c0429fcc>] (clk_disable) from [<c059cbd0>] (ad9371_profile_bin_write+0x29c/0x17c0)
[  417.991733] [<c059cbd0>] (ad9371_profile_bin_write) from [<c02a6fa4>] (sysfs_kf_bin_write+0x84/0x9c)
[  418.000827] [<c02a6fa4>] (sysfs_kf_bin_write) from [<c02a6668>] (kernfs_fop_write+0x104/0x208)
[  418.009403] [<c02a6668>] (kernfs_fop_write) from [<c02385c8>] (__vfs_write+0x38/0x128)
[  418.017288] [<c02385c8>] (__vfs_write) from [<c0239454>] (vfs_write+0xb4/0x178)
[  418.024566] [<c0239454>] (vfs_write) from [<c023a26c>] (SyS_write+0x4c/0xa0)
[  418.031586] [<c023a26c>] (SyS_write) from [<c0108080>] (ret_fast_syscall+0x0/0x3c)
[  418.039118] ---[ end trace 28be9184bed701b5 ]---
[  418.043750] ------------[ cut here ]------------
[  418.048361] WARNING: CPU: 0 PID: 911 at drivers/clk/clk.c:504 clk_core_unprepare+0xbc/0x1a4
[  418.056704] Modules linked in: mwipcore mwipcore_iio_streaming mwipcore_iio_mm mwipcore_dma_streaming mathworks_ip_common
[  418.067700] CPU: 0 PID: 911 Comm: cat Tainted: G        W       4.9.0 #2
[  418.074367] Hardware name: Altera SOCFPGA Arria10
[  418.079061] [<c01110e0>] (unwind_backtrace) from [<c010caec>] (show_stack+0x20/0x24)
[  418.086774] [<c010caec>] (show_stack) from [<c03e839c>] (dump_stack+0x98/0xac)
[  418.093966] [<c03e839c>] (dump_stack) from [<c011fe50>] (__warn+0xf8/0x110)
[  418.100897] [<c011fe50>] (__warn) from [<c011ff38>] (warn_slowpath_null+0x30/0x38)
[  418.108434] [<c011ff38>] (warn_slowpath_null) from [<c04298d0>] (clk_core_unprepare+0xbc/0x1a4)
[  418.117094] [<c04298d0>] (clk_core_unprepare) from [<c042ab10>] (clk_unprepare+0x34/0x3c)
[  418.125238] [<c042ab10>] (clk_unprepare) from [<c059cbd8>] (ad9371_profile_bin_write+0x2a4/0x17c0)
[  418.134160] [<c059cbd8>] (ad9371_profile_bin_write) from [<c02a6fa4>] (sysfs_kf_bin_write+0x84/0x9c)
[  418.143254] [<c02a6fa4>] (sysfs_kf_bin_write) from [<c02a6668>] (kernfs_fop_write+0x104/0x208)
[  418.151829] [<c02a6668>] (kernfs_fop_write) from [<c02385c8>] (__vfs_write+0x38/0x128)
[  418.159714] [<c02385c8>] (__vfs_write) from [<c0239454>] (vfs_write+0xb4/0x178)
[  418.166992] [<c0239454>] (vfs_write) from [<c023a26c>] (SyS_write+0x4c/0xa0)
[  418.174013] [<c023a26c>] (SyS_write) from [<c0108080>] (ret_fast_syscall+0x0/0x3c)
[  418.181599] ---[ end trace 28be9184bed701b6 ]---
[  418.186205] ------------[ cut here ]------------
[  418.190808] WARNING: CPU: 0 PID: 911 at drivers/clk/clk.c:622 clk_core_disable+0xb0/0x194
[  418.198943] Modules linked in: mwipcore mwipcore_iio_streaming mwipcore_iio_mm mwipcore_dma_streaming mathworks_ip_common
[  418.209916] CPU: 0 PID: 911 Comm: cat Tainted: G        W       4.9.0 #2
[  418.216582] Hardware name: Altera SOCFPGA Arria10
[  418.221271] [<c01110e0>] (unwind_backtrace) from [<c010caec>] (show_stack+0x20/0x24)
[  418.228981] [<c010caec>] (show_stack) from [<c03e839c>] (dump_stack+0x98/0xac)
[  418.236172] [<c03e839c>] (dump_stack) from [<c011fe50>] (__warn+0xf8/0x110)
[  418.243102] [<c011fe50>] (__warn) from [<c011ff38>] (warn_slowpath_null+0x30/0x38)
[  418.250638] [<c011ff38>] (warn_slowpath_null) from [<c0429bec>] (clk_core_disable+0xb0/0x194)
[  418.259125] [<c0429bec>] (clk_core_disable) from [<c0429f94>] (clk_core_disable_lock+0x28/0x34)
[  418.267784] [<c0429f94>] (clk_core_disable_lock) from [<c0429fcc>] (clk_disable+0x2c/0x30)
[  418.276012] [<c0429fcc>] (clk_disable) from [<c059cbe4>] (ad9371_profile_bin_write+0x2b0/0x17c0)
[  418.284760] [<c059cbe4>] (ad9371_profile_bin_write) from [<c02a6fa4>] (sysfs_kf_bin_write+0x84/0x9c)
[  418.293852] [<c02a6fa4>] (sysfs_kf_bin_write) from [<c02a6668>] (kernfs_fop_write+0x104/0x208)
[  418.302427] [<c02a6668>] (kernfs_fop_write) from [<c02385c8>] (__vfs_write+0x38/0x128)
[  418.310309] [<c02385c8>] (__vfs_write) from [<c0239454>] (vfs_write+0xb4/0x178)
[  418.317586] [<c0239454>] (vfs_write) from [<c023a26c>] (SyS_write+0x4c/0xa0)
[  418.324605] [<c023a26c>] (SyS_write) from [<c0108080>] (ret_fast_syscall+0x0/0x3c)
[  418.332136] ---[ end trace 28be9184bed701b7 ]---
[  418.336754] ------------[ cut here ]------------
[  418.341358] WARNING: CPU: 0 PID: 911 at drivers/clk/clk.c:504 clk_core_unprepare+0xbc/0x1a4
[  418.349680] Modules linked in: mwipcore mwipcore_iio_streaming mwipcore_iio_mm mwipcore_dma_streaming mathworks_ip_common
[  418.360665] CPU: 0 PID: 911 Comm: cat Tainted: G        W       4.9.0 #2
[  418.367332] Hardware name: Altera SOCFPGA Arria10
[  418.372020] [<c01110e0>] (unwind_backtrace) from [<c010caec>] (show_stack+0x20/0x24)
[  418.379730] [<c010caec>] (show_stack) from [<c03e839c>] (dump_stack+0x98/0xac)
[  418.386920] [<c03e839c>] (dump_stack) from [<c011fe50>] (__warn+0xf8/0x110)
[  418.393851] [<c011fe50>] (__warn) from [<c011ff38>] (warn_slowpath_null+0x30/0x38)
[  418.401387] [<c011ff38>] (warn_slowpath_null) from [<c04298d0>] (clk_core_unprepare+0xbc/0x1a4)
[  418.410047] [<c04298d0>] (clk_core_unprepare) from [<c042ab10>] (clk_unprepare+0x34/0x3c)
[  418.418189] [<c042ab10>] (clk_unprepare) from [<c059cbec>] (ad9371_profile_bin_write+0x2b8/0x17c0)
[  418.427109] [<c059cbec>] (ad9371_profile_bin_write) from [<c02a6fa4>] (sysfs_kf_bin_write+0x84/0x9c)
[  418.436199] [<c02a6fa4>] (sysfs_kf_bin_write) from [<c02a6668>] (kernfs_fop_write+0x104/0x208)
[  418.444774] [<c02a6668>] (kernfs_fop_write) from [<c02385c8>] (__vfs_write+0x38/0x128)
[  418.452657] [<c02385c8>] (__vfs_write) from [<c0239454>] (vfs_write+0xb4/0x178)
[  418.459935] [<c0239454>] (vfs_write) from [<c023a26c>] (SyS_write+0x4c/0xa0)
[  418.466954] [<c023a26c>] (SyS_write) from [<c0108080>] (ret_fast_syscall+0x0/0x3c)
[  418.474502] ---[ end trace 28be9184bed701b8 ]---
[  418.479102] ------------[ cut here ]------------
[  418.483703] WARNING: CPU: 0 PID: 911 at drivers/clk/clk.c:622 clk_core_disable+0xb0/0x194
[  418.491839] Modules linked in: mwipcore mwipcore_iio_streaming mwipcore_iio_mm mwipcore_dma_streaming mathworks_ip_common
[  418.502809] CPU: 0 PID: 911 Comm: cat Tainted: G        W       4.9.0 #2
[  418.509476] Hardware name: Altera SOCFPGA Arria10
[  418.514162] [<c01110e0>] (unwind_backtrace) from [<c010caec>] (show_stack+0x20/0x24)
[  418.521871] [<c010caec>] (show_stack) from [<c03e839c>] (dump_stack+0x98/0xac)
[  418.529062] [<c03e839c>] (dump_stack) from [<c011fe50>] (__warn+0xf8/0x110)
[  418.535992] [<c011fe50>] (__warn) from [<c011ff38>] (warn_slowpath_null+0x30/0x38)
[  418.543528] [<c011ff38>] (warn_slowpath_null) from [<c0429bec>] (clk_core_disable+0xb0/0x194)
[  418.552014] [<c0429bec>] (clk_core_disable) from [<c0429f94>] (clk_core_disable_lock+0x28/0x34)
[  418.560673] [<c0429f94>] (clk_core_disable_lock) from [<c0429fcc>] (clk_disable+0x2c/0x30)
[  418.568901] [<c0429fcc>] (clk_disable) from [<c059cbf8>] (ad9371_profile_bin_write+0x2c4/0x17c0)
[  418.577649] [<c059cbf8>] (ad9371_profile_bin_write) from [<c02a6fa4>] (sysfs_kf_bin_write+0x84/0x9c)
[  418.586741] [<c02a6fa4>] (sysfs_kf_bin_write) from [<c02a6668>] (kernfs_fop_write+0x104/0x208)
[  418.595316] [<c02a6668>] (kernfs_fop_write) from [<c02385c8>] (__vfs_write+0x38/0x128)
[  418.603199] [<c02385c8>] (__vfs_write) from [<c0239454>] (vfs_write+0xb4/0x178)
[  418.610475] [<c0239454>] (vfs_write) from [<c023a26c>] (SyS_write+0x4c/0xa0)
[  418.617494] [<c023a26c>] (SyS_write) from [<c0108080>] (ret_fast_syscall+0x0/0x3c)
[  418.625027] ---[ end trace 28be9184bed701b9 ]---
[  418.629635] ------------[ cut here ]------------
[  418.634250] WARNING: CPU: 0 PID: 911 at drivers/clk/clk.c:504 clk_core_unprepare+0xbc/0x1a4
[  418.642568] Modules linked in: mwipcore mwipcore_iio_streaming mwipcore_iio_mm mwipcore_dma_streaming mathworks_ip_common
[  418.653549] CPU: 0 PID: 911 Comm: cat Tainted: G        W       4.9.0 #2
[  418.660217] Hardware name: Altera SOCFPGA Arria10
[  418.664904] [<c01110e0>] (unwind_backtrace) from [<c010caec>] (show_stack+0x20/0x24)
[  418.672613] [<c010caec>] (show_stack) from [<c03e839c>] (dump_stack+0x98/0xac)
[  418.679803] [<c03e839c>] (dump_stack) from [<c011fe50>] (__warn+0xf8/0x110)
[  418.686733] [<c011fe50>] (__warn) from [<c011ff38>] (warn_slowpath_null+0x30/0x38)
[  418.694271] [<c011ff38>] (warn_slowpath_null) from [<c04298d0>] (clk_core_unprepare+0xbc/0x1a4)
[  418.702930] [<c04298d0>] (clk_core_unprepare) from [<c042ab10>] (clk_unprepare+0x34/0x3c)
[  418.711072] [<c042ab10>] (clk_unprepare) from [<c059cc00>] (ad9371_profile_bin_write+0x2cc/0x17c0)
[  418.719992] [<c059cc00>] (ad9371_profile_bin_write) from [<c02a6fa4>] (sysfs_kf_bin_write+0x84/0x9c)
[  418.729084] [<c02a6fa4>] (sysfs_kf_bin_write) from [<c02a6668>] (kernfs_fop_write+0x104/0x208)
[  418.737659] [<c02a6668>] (kernfs_fop_write) from [<c02385c8>] (__vfs_write+0x38/0x128)
[  418.745542] [<c02385c8>] (__vfs_write) from [<c0239454>] (vfs_write+0xb4/0x178)
[  418.752818] [<c0239454>] (vfs_write) from [<c023a26c>] (SyS_write+0x4c/0xa0)
[  418.759838] [<c023a26c>] (SyS_write) from [<c0108080>] (ret_fast_syscall+0x0/0x3c)
[  418.767401] ---[ end trace 28be9184bed701ba ]---
[  420.095650] ERROR: 64: CLKPLL VCO frequency exceeded max(9.216Ghz) in VCO divider /1.5 case ()
[  420.104241] ERROR: 64: CLKPLL VCO frequency exceeded max(9.216Ghz) in VCO divider /1.5 case ()
[  420.112833] ad9371 spi32766.1: CLKPLL VCO frequency exceeded max(9.216Ghz) in VCO divider /1.5 case ()
[  420.112833]  (64)
[  421.445844] ERROR: 64: CLKPLL VCO frequency exceeded max(9.216Ghz) in VCO divider /1.5 case ()
[  421.454430] ERROR: 64: CLKPLL VCO frequency exceeded max(9.216Ghz) in VCO divider /1.5 case ()
[  421.463021] ad9371 spi32766.1: CLKPLL VCO frequency exceeded max(9.216Ghz) in VCO divider /1.5 case ()
[  421.463021]  (64)

Nevertheless, if I use the other (second) pair for coefficients (Filter Wiz pick up ONLY the first pair), it works fine (see the other profile). That was an exact fix to .m file for Filter Wiz I have implemented.

<profile AD9371 version=0 name=Rx 40, IQrate 80.000>
 <clocks>
  <deviceClock_kHz=320000>
  <clkPllVcoFreq_kHz=9600000>
  <clkPllVcoDiv=1.5>
  <clkPllHsDiv=4>
 </clocks>

 <rx>
  <adcDiv=1>
  <rxFirDecimation=2>
  <rxDec5Decimation=5>
  <enHighRejDec5=1>
  <rhb1Decimation=2>
  <iqRate_kHz=80000>
  <rfBandwidth_Hz=40000000>
  <rxBbf3dBCorner_kHz=40000>

  <filter FIR gain=-6 num=72>
  -9
  12
  18
  17
  -17
  -49
  -45
  21
  99
  105
  -11
  -171
  -215
  -36
  258
  390
  149
  -343
  -648
  -371
  394
  1003
  763
  -357
  -1476
  -1425
  138
  2113
  2589
  489
  -3082
  -5079
  -2537
  4990
  14500
  21095
  21095
  14500
  4990
  -2537
  -5079
  -3082
  489
  2589
  2113
  138
  -1425
  -1476
  -357
  763
  1003
  394
  -371
  -648
  -343
  149
  390
  258
  -36
  -215
  -171
  -11
  105
  99
  21
  -45
  -49
  -17
  17
  18
  12
  -9
  </filter>

  <adc-profile num=16>
  460
  273
  182
  98
  1280
  112
  1505
  53
  1574
  25
  1069
  40
  48
  48
  31
  184
  </adc-profile>
 </rx>

 <obs>
  <adcDiv=1>
  <rxFirDecimation=2>
  <rxDec5Decimation=5>
  <enHighRejDec5=1>
  <rhb1Decimation=2>
  <iqRate_kHz=80000>
  <rfBandwidth_Hz=40000000>
  <rxBbf3dBCorner_kHz=20000>

  <filter FIR gain=-6 num=72>
  -18
  15
  27
  32
  -16
  -69
  -77
  14
  137
  167
  13
  -229
  -325
  -95
  336
  572
  273
  -432
  -928
  -606
  470
  1411
  1178
  -369
  -2041
  -2133
  -21
  2861
  3799
  1074
  -4039
  -7463
  -5019
  4166
  16265
  24784
  24784
  16265
  4166
  -5019
  -7463
  -4039
  1074
  3799
  2861
  -21
  -2133
  -2041
  -369
  1178
  1411
  470
  -606
  -928
  -432
  273
  572
  336
  -95
  -325
  -229
  13
  167
  137
  14
  -77
  -69
  -16
  32
  27
  15
  -18
  </filter>

  <adc-profile num=16>
  460
  273
  182
  98
  1280
  112
  1505
  53
  1574
  25
  1069
  40
  48
  48
  31
  184
  </adc-profile>

  <lpbk-adc-profile num=16>
  460
  273
  182
  98
  1280
  112
  1505
  53
  1574
  25
  1069
  40
  48
  48
  31
  184
  </lpbk-adc-profile>
 </obs>

 <tx>
  <dacDiv=2.5>
  <txFirInterpolation=2>
  <thb1Interpolation=2>
  <thb2Interpolation=2>
  <txInputHbInterpolation=1>
  <iqRate_kHz=80000>
  <primarySigBandwidth_Hz=20000000>
  <rfBandwidth_Hz=40000000>
  <txDac3dBCorner_kHz=92000>
  <txBbf3dBCorner_kHz=20000>

  <filter FIR gain=0 num=32>
  -4
  2
  37
  -6
  -183
  -34
  603
  261
  -1596
  -1164
  3511
  4466
  -4555
  -10628
  2571
  23092
  23092
  2571
  -10628
  -4555
  4466
  3511
  -1164
  -1596
  261
  603
  -34
  -183
  -6
  37
  2
  -4
  </filter>
 </tx>
</profile>

<profile AD9371 version=0 name=Rx 40, IQrate 80.000>
 <clocks>
  <deviceClock_kHz=320000>
  <clkPllVcoFreq_kHz=9600000>
  <clkPllVcoDiv=3>
  <clkPllHsDiv=4>
 </clocks>

 <rx>
  <adcDiv=1>
  <rxFirDecimation=2>
  <rxDec5Decimation=5>
  <enHighRejDec5=1>
  <rhb1Decimation=1>
  <iqRate_kHz=80000>
  <rfBandwidth_Hz=40000000>
  <rxBbf3dBCorner_kHz=40000>

  <filter FIR gain=-6 num=48>
  1
  7
  3
  -20
  -38
  10
  107
  100
  -122
  -334
  -113
  506
  718
  -166
  -1391
  -1095
  1231
  3033
  981
  -4224
  -6482
  219
  14325
  26107
  26107
  14325
  219
  -6482
  -4224
  981
  3033
  1231
  -1095
  -1391
  -166
  718
  506
  -113
  -334
  -122
  100
  107
  10
  -38
  -20
  3
  7
  1
  </filter>

  <adc-profile num=16>
  900
  559
  201
  98
  1280
  199
  1522
  98
  860
  25
  529
  37
  48
  26
  15
  196
  </adc-profile>
 </rx>

 <obs>
  <adcDiv=1>
  <rxFirDecimation=2>
  <rxDec5Decimation=5>
  <enHighRejDec5=1>
  <rhb1Decimation=1>
  <iqRate_kHz=80000>
  <rfBandwidth_Hz=40000000>
  <rxBbf3dBCorner_kHz=20000>

  <filter FIR gain=-6 num=48>
  -1
  10
  10
  -22
  -60
  -6
  143
  171
  -129
  -485
  -245
  660
  1099
  -74
  -1954
  -1784
  1506
  4443
  1920
  -5737
  -10210
  -2631
  15550
  31189
  31189
  15550
  -2631
  -10210
  -5737
  1920
  4443
  1506
  -1784
  -1954
  -74
  1099
  660
  -245
  -485
  -129
  171
  143
  -6
  -60
  -22
  10
  10
  -1
  </filter>

  <adc-profile num=16>
  900
  559
  201
  98
  1280
  199
  1522
  98
  860
  25
  529
  37
  48
  26
  15
  196
  </adc-profile>

  <lpbk-adc-profile num=16>
  922
  550
  201
  98
  1280
  112
  1505
  53
  864
  14
  533
  40
  48
  26
  15
  197
  </lpbk-adc-profile>
 </obs>

 <sniffer>
  <adcDiv=1>
  <rxFirDecimation=2>
  <rxDec5Decimation=5>
  <enHighRejDec5=1>
  <rhb1Decimation=2>
  <iqRate_kHz=40000>
  <rfBandwidth_Hz=20000000>
  <rxBbf3dBCorner_kHz=20000>

  <filter FIR gain=-6 num=72>
  -9
  12
  18
  17
  -17
  -49
  -45
  21
  99
  105
  -11
  -171
  -215
  -36
  258
  390
  149
  -343
  -648
  -371
  394
  1003
  763
  -357
  -1476
  -1425
  138
  2113
  2589
  489
  -3082
  -5079
  -2537
  4990
  14500
  21095
  21095
  14500
  4990
  -2537
  -5079
  -3082
  489
  2589
  2113
  138
  -1425
  -1476
  -357
  763
  1003
  394
  -371
  -648
  -343
  149
  390
  258
  -36
  -215
  -171
  -11
  105
  99
  21
  -45
  -49
  -17
  17
  18
  12
  -9
  </filter>

  <adc-profile num=16>
  922
  550
  201
  98
  1280
  112
  1505
  53
  864
  14
  533
  40
  48
  26
  15
  197
  </adc-profile>
 </sniffer>

 <tx>
  <dacDiv=2.5>
  <txFirInterpolation=1>
  <thb1Interpolation=2>
  <thb2Interpolation=2>
  <txInputHbInterpolation=1>
  <iqRate_kHz=80000>
  <primarySigBandwidth_Hz=20000000>
  <rfBandwidth_Hz=40000000>
  <txDac3dBCorner_kHz=92000>
  <txBbf3dBCorner_kHz=20000>

  <filter FIR gain=6 num=16>
  26
  -292
  -75
  333
  339
  -659
  -2192
  21034
  -2192
  -659
  339
  333
  -75
  -292
  26
  0
  </filter>
 </tx>
</profile>

It been a week since my last post, I just want to ping to see where we going.

Main equation is why driver is failing at initial calibration of TX and how to avoid it.

 (otherwise I have to wait for 60 sec for calibration time out)

Many thanks in advance.

It been a week since my last post, I just want to ping to see where we going.

Main equation is why driver is failing at initial calibration of TX and how to avoid it.

 (otherwise I have to wait for 60 sec for calibration time out)

Many thanks in advance.

Sorry for the delay in response.

How are you generating the second profile which you have attached? There are differences in the hb1 decimation and the clkpll vco divider. If you are changing the decimation values manually then the sample rate will also change which will lead to error.Please use the filter wizard for generating custom profile and without any manual change to it load that profile in the GUI.

Hope you are giving a proper reference clock corresponding to VCXO of 80MHz and dev clock of 80Mhz

Please use the AD9528 GUI for better understanding which can be downloaded from the below link:

https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD9528.html#eb-relatedsoftware

Perhaps it is better to get one step back. As I wrote in the begging of previous email @Jan 23:

"I generate a profile using Filter Wiz. For 80Msps (see setting on .jpg image)

If I load this profile, I get following error (which is correct, this settings are not supported by AD9371 PLL)."

Hence, what you are sking, "Please use the filter wizard for generating custom profile and without any manual change to it load that profile in the GUI", is alredy done and does not work.

So, without contaminating this result with my fixes, could you tell me why a custom profile generated with the filter wizard is given an error? All settings for custom profile and generated file are included in my post on Jan 23.

Note that I provide a proper device clk (320MHz) from AD9528 by modifying setting in dts file and verified a clock frequency using scope.

Hello,

Just want to ping regarding you answer to my last post, would you be able to help?

As a brief re-cap, I generate a profile for 80MHz sampling rate using Filter Wizard (device clk is already adjusted and verified) but it is not valid when I load it to the board.

Thanks in advance for your help,

Mikhail

Sorry for delay in response. We were debugging this internally and hence it took some time.

There is an issue with the profile generator as well as the software for the 80MHz profile specially with a  clkpll vco divider setting of 1.5.

You can generate the same profile and  load it but with a clkPLL VCO divider value of 3 instead of 1.5 and then program it.You are already doing that with your own fixes.So you can use that and for 1.5 we have reported the issue with design team and it may take some time for a fix.

Hello,

Thank you for your response and clarifications – very much appreciated.

Yes, I was doing exactly what your subjected (generate a profile with a clkPLL VCO divider value of 3).

Using this profile settings, I modify .dts file (it was included in the post earlier), but driver is failing TX QEC INIT calibration after time out of 60 sec. (if I disable TX QEC INIT calibration and load the same profile after that everything works fine)

Could you subject the next steps to resolve issue with TX QEC INIT calibration?

Thanks in advance,

Mikhail

Yes we are also seeing the same issue.  TXQEC init cal fails with the  profile(80Msps sampling rate)

We are discussing that internally. Will let you know once we get a fix for it.

Hello,

Just want to ping regarding your answer to my last post, would you be able to help?

Thanks in advance for your help,

Mikhail

Is there a solution to this problem?

Please refer to the below posts for the workaround, If you are still facing issues kindly let us know.

https://ez.analog.com/wide-band-rf-transceivers/tes-gui-and-api-software-ad9371-ad9375/f/q-a/80805/when-i-load-my-matlab-generated-profile-in-tes-and-generate-c-code-initialization-scripts-the-board-pll-doesn-t-lock

https://ez.analog.com/wide-band-rf-transceivers/tes-gui-and-api-software-ad9371-ad9375/f/q-a/80747/ad9371-custom-profile-calibration-error

Did this get fixed in the profile generator? I'm seeing this problem for 80 MHz as well.