Why use a PLL architecture that supports High Voltage VCOs?
Although Analog Devices makes PLLs such as the ADF4350 which include integrated low-phase-noise VCOs, for very demanding phase noise or higher frequency applications an external VCO is often the only way to go.
For a VCO, the higher its gain (Kv) the higher the VCO noise. So VCO designers will tend to use a low to medium gain (e.g. from 5MHz/V to 70MHz/V) to optimise noise. To get a good useable frequency range a wide tuning range is often required (e.g. from 1V to 12V).
Analog Devices' PLLs typically tune up to about 5V. So an active filter (i.e. Op-Amp) is typically used to interface and level-shift the PLL charge pump output to the higher VCO tuning voltages necessary. ADIsimPLL supports several active filter topologies to help in designing these stages. Active filter stages, however, tend to add noise and/or spurious content. For a non-inverting stage, generating a low-noise bias voltage is not trivial.
The alternative to active filters is to use a PLL which can directly output charge pump voltages as high as 15V or even 30V. The ADF4113HV and the new ADF4150HV are examples of these. High voltage PLLs eliminate active filter stage. The use of a standard low-noise passive loop filter means the phase noise can be improved compared to an active filter stage.
Check this Analog Dialogue article "Designing High-Performance Phase-Locked Loops with High-Voltage VCOs" for a more detailed discussion on active loop filter design and trade-offs.
Dear App. Eng,
My DDS driven synth started to work.
Unfortunately this one is more noisier than I have made 4 years ago.
( System was: 100 MHz low noise XTAL ref. osc., AD9951, ADF4001, OP27, 4 jFET Hartley VCO)
I have to check where the noise come from. I think the DDS out as a PLL reference would be a main
noise source. In this system I use a 24MHz XTAL, internal osc . in AD9951, 6x internal PLL -> 144MHz as
DDS System Reference ->6...13.6MHz DDS OUT -> LPF -> ADCMP600 -> ADF4150HV (R=1, N=23 INT N mode, 20kHz loop BW) -> 4 BFR93 Clapp VCO.
Test System is R&S FSP3. Measured phase noise is -90dBc @ 296MHz.
Q: How can I optimize the AD9951 PLL Loop Filter for 6x multiplication?
Datasheet offer a 100nF + 1k loop filter. Is it good for all 4x..20x multiplication range?
The AD9951 is a derivative of the AD9954. So, SFDR, phase nosie, PLL operation should be the same. So, the die is the same, the only difference is bond options to disable features between the two device products. That said, the AD9954 data sheet has more information for some reason about the external loop filter values. See table 4 page 13 in the AD9954 data sheet.
I modefied loop filter based on information found in AD9954 data sheet. Thank's for info!
There was no any sigificant changes in phase-noise.
I used a 10MHz REF_OUT of FSP3 analyzer for PLL reference.
The in-band phase-noise decreesed by 6dB measured on VCO buffer output.
Q1: What would be an absolute phase-noise of DDS out in following system? Internal XTAL OSC+ 24MHz 5x3mm XTAL, 6x REFCLK_MULT (=144MHz SYS_CLK), 10MHz out.
Originally I connect 27pF tuning capacitors of XTAL to DDS_AVDD.
Q2: What is the better sollution, if capacitors is connected to DDS_AVDD or GND?
Q3: How many Voltage is enough for good operation measured on XTAL's pins?