The ADL5802 datasheet states that the device is capable of operation to frequencies as low as 100 MHz, yet the Typical Performance Characteristics plots only show data as low as 500 MHz. Is the device capable of operation at these low frequencies and is there any typical performance data available?
The ADL5802 is indeed capable of operating at frequencies as low as 100 MHz and below. In order to achieve low frequency operation some changes are necessary to the standard evaluation board. Specifically, the RF series input capacitors (C5, C12, C13 & C14) should be changed from their datasheet recommended value of 100pF to a higher value of 1nF. The lower capacitor values create a highpass filter effect on the input resulting in poor return loss at low frequency which should be avoided.
The performance of the ADL5802 was characterized for IF frequencies of 10 MHz and 70 MHz in Low Side LO and High Side LO configurations. The typical performance of the ADL5802 can be seen in the attached plots.
The standard ADL5802 evaluation board configuration was used. Capacitors C5, C12, C13 & C14 were replaced with 1nF capacitors. VS=5V, VSET=3.8V, unless otherwise noted. The 4:1 IF port transformer (TC4-1W+), the RF and LO port transformers ( TC1-1-13M+) and PCB loss are included in the measurement.
Summary: The ADL5802 under low frequencies indicates the following typical performance: Gain = 0.6dB (Balun and PCB loss inclusive), IIP3 = 33dBm, IIP2 = 70dBm, P1dB = 13dBm and Noise Figure = 11dB.
If I understand correctly, MickOC was saying that the ADL5802 datasheet low-frequency limit (especially at the RF port) was determined by the limited performance of the passive components used on the evaluation PCB and has nothing to do with the performance of the ADI part itself. (If so, I expect this is limiting sales of the part unnecessarily!)
I am interested in using a down-converting mixer with RF input that can be swept over the frequency range <10kHz - 4GHz for a piece of test equipment (similar to a VNA with integrated test-set), with a ~5kHz IF, amplified with an AD8253 and digitised by an AD7608. In order to ensure clean switching of the mixer core even at low frequencies, I would drive the LO port with a square wave LO signal.
In order to do this over an extremely broad frequency range and to avoid settling time for huge coupling capacitors, I would prefer to DC-couple the LO port to the source which would be a LVPECL clock buffer, (e.g. ADCLK948, perhaps running from an unusual supply voltage and/or with resistive dividers to shift the DC level at the output). Presumably it would be necessary to shift the DC level of the LO signal to be equal to the DC bias voltage that the ADL5802 would normally generate internally. Whilst finding this voltage by experiment should be feasible, any information you could provide about what level to choose would be much appreciated.
Similarly, I would like to drive the RF input without AC-coupling capacitors (but biased to some carefully chosen voltage that the ADL5802 is happy with), because an input capacitor would limit the low-frequency operation and/or introduce long settling times. I am not concerned about noise figure and linearity of the mixer as I can choose the input amplitude to be as large or small as I want, but I am interested in broadband operation and gain that is fairly stable and repeatable, so I would use resistive pads for any impedance matching.
I am also very interested in two-port s-parameters of the two pins for the RF input port, (of the chip, without any balun) because in my application I would drive the two sides the differential input with separate single-ended signals in order to perform a vector subtraction of the signals without the cost of additional parts. (I understand that this is not the ideal way to do this, but cost and PCB complexity matters in this application.) If each input has a mostly single-ended termination on-chip then that would be fine, and the coupling between the adjacent bondwires shouldn't be enough to be a problem. If the on-chip termination were mostly connected differentially between the input pins then this might not work so well in my application. Looking at the related part ADL5801, there was a post with s-parameters, it looks like the inputs are not strongly coupled mag(S12) and mag(S21) are below 0.32 for all frequencies:
So I think I just need to get the DC level right.
I had been planning to use the LT5560 for this task as it seems to have a nice common-base buffer at the RF-input, however the ADL5802 might be even better as it will give me the two channels that I require per test-set in one chip, (saving parts count and improving LO phase matcing between channels), and the integrated LO buffer may help in achieving clean fast LO edges at the mixer cores, and the ADL5802 is specified for 6GHz operation which would be an advantage.
So, if you could please provide any advice on driving the LO-port from a DC-shifted LVPECL signal that would be appreciated, and any help with the correct voltage to bias the RF input signals at, if they are driven from 50 Ohm DC-coupled signals (referenced to whatever DC voltage is best), would also be appreciated. Ideally, it would be really nice to see the (maybe simplified) schematic of the input circuit at the RF and LO pins, similar to what is provided in the LT5560 datasheet, if you are allowed to provide that. Any other S-parameter files that you already have for the chip without baluns would of course be nice too!