The phase noise in an PLL can be described as having 2 components as shown in figure.1, a flat noise component known as the PLL Noise Floor, and a flicker 1/f Noise known as the PLL 1/f Noise.
To reflect this in our datasheets, we have broken out our PLL phase noise specifications into two separate specifications, a Normalized phase noise floor (PNSYNTH), and a Normalized 1/f Noise (PN1_f).
PLL Noise Floor (PNTOT1)
PNTOT1 = PNSYNTH + 20Log(N) + 10Log(FPFD) (1)
PNSYNTH (normalised noise floor in a 1Hz bandwidth) is very much device specific. N is the divider used by the PLL and FPFD is the frequency of the phase frequency detector.
In order to accurately capture both PLL noise components, the loop bandwidth used to measure the PLL noise floor is 500kHz or greater. The VCO noise is high pass filtered inside the loop bandwidth, therefore using a wide instead of a narrow loop bandwidth will push more of the VCO noise out of band.
PNTOT1( phase noise floor )is measured at an offset of 100kHz or greater. PNSYNTH (Normalized phase noise floor) is then easily calculated by removing the 20Log(N) and the 10Log(FPFD) contributions, see equation (1).
For wide loop bandwidths, the normalized phase noise floor is the dominant PLL noise source.
PLL 1/f Noise (PNTOT2)
PNTOT2 = PN1/f + 20Log(FRF/1GHz) + 10Log(10kHz/f) (2)
FRF is the o/p RF frequency, and f = 1KHz(offset frequency where we measure PNTOT2).
PNTOT2 (PLL 1/f noise) is measured at an offset of 1KHz. PN1/f (Normalized 1/f noise) is then calculated by removing the 20Log(FRF/1GHz) and the 10Log(10kHz/f) contributions, see equation (2).
Active devices, including the PLL charge pump, produce a flicker (1/f) noise.
Equation (2) indicates that the PLL 1/f noise increases 20dBs per decade as a function of FRF and 10 dBs per decade as a function of f (offset frequency from the carrier).
For narrow loop bandwidths, the normalized 1/f noise number is significant.
These noise sources add together, giving a total PLL phase noise. Since noise sources add in root sum fashion, the larger noise source will dominate.
ADIsimPLL Version3.3 and greater models both the noise floor and 1/f noise so you can accurately simulate PLL phase noise for the PLL loop design.