List of Abbreviations
If you could not find what you need on the FAQ, please read `Amplifier Product Application Notes` on the following link.
And watch `Distributed Amplifier Biasing and Optimization` video on below link.
Q1. HMCxxx amplifier has multiple Vdd and Vgg connetions. Can I tie them together?
A1. Each HMC AMP, has an Evaluation PCB, i.e. EVB drawing provided on the datasheet.
The `Application Circuit` for that EVB is also given on the datasheet. Refer to `Figure-1`.
Figure -1: An example AMP AC.
The AMP IC itself is characterised using EVB and AC given on the DS.
You can connect all Vdds together unless otherwise stated on the DS.
Q2. HMCxxx AMP`s AC has multiple bypass CAPs on Vdd, Vgg supply pins. Can I reduce the CAP count?
A2. Unless otherwise stated, the AMP IC itself is characterised using EVB and AC configuration given on the DS. Sticking with DS configuration will help on getting performance curves like the ones on the DS.
It is not possible to cover all application needs by one EVB, so we aim to define an AC configuration that can cover the most; and help ourselves and our customers to evaluate the AMP`s performance easier.
Main purpose of the CAPs on Vdd and Vgg lines is filtering the noise on DC sources. Some applications use high performance LDOs with pure and precise outputs. Then you may not need to use all shunt CAPs on supply lines. But if your PSU unit has poor performance you may even need more.
Below plot shows typical reactance vs frequency response of some CAP values. The idea is to have low impedance among wide frequency range, so combining different value of CAPs together helps achieving this goal.
3 pF CAP on the MMIC is a typical value and will vary among different AMPs.
Figure - 2: Capacitor Self Resonance Magnitude of REactance vs Frequency
Q3-B. Can I tie Vdd pins together and then reduce the CAP count?
A3-B. In reference to `Figure-1`, there are 4.7 uF, 10 nF and 100 pF CAPs on each supply line. Sometimes due to space restrictions, Vdd pins are tied together and only one 4.7 uF tantalum CAP is used. Same can be done for the 10 nF CAP. As a rule of thumb it would be nice to use 100 pF on each pin. CAP values for each AMP can change, and given on their DS.
As stated on `A3`,
Unless otherwise stated, the AMP IC itself is characterised using EVB and AC configuration given on the DS. Sticking with DS configuration will help on getting performance curves like the ones on the DS.
Q3-C. Some HMC AMPs have ACG pins, can I remove the ACG caps on
AC-3. AC GND pins generally exist on wideband AMPs. Removing AC GND CAPs can cause gain increase at lower frequencies and introduce gain ripple among the frequency range. Furthermore, return loss can degrade. So it is best to further evaluate. If the AMP`s performance change is still within your application requirements, than you can pursue with the new AC configuration.
Figure 3 - Distributed AMP AC
Q4. Some of the HMC AMPs need bias tee to supply bias voltages to the RF I/O pin(s). Do you have recommendations for bias-tee circuits?
A4. Bias tee`s are generally combination of DC block and RF choke inductors. Depending on the frequency of operation, those CAP and inductor values should be calculated.
Refer to the Application Note on the following link.
And it is best to check the performance of the bias-tee with real world components, using a VNA and a connectorized 50-ohm thru line.
Q5. Some of the HMC AMPs have Vgg pins. What should I do with that?
Non self-biased amplifiers have a note below the electrical spec table saying,
``* Adjust Vgg1 between -`X` to `Y` V to achieve Idd = `Z` mA typical``
You need adjust Vgg to get the quiescent Idd value provided on the datasheet. Best way to do this is using an Active Bias Controller circuit to form a feedback loop that adjusts Vgg constantly to get desired Idd.
An example ABC circuit to bias an example amplifier can be found on the following link.
ADI also has `Active Bias Controllers` product line to bias these kind of amplifiers, can be found on below link.
By using ABC products, you can,
Q5-B: Can I use a simple resistive divider to set Vgg1?
A5-B: There is no restriction on using a resistive divider to set Vgg. However, by doing that, you will be avoiding your chance of, reducing the effects or part to part variation between amplifiers. And you will introduce the tolerance and variations of resistors into your circuit.
Q5-C: Can I use a simple resistive divider to set Vgg2?
A5-C: Yes, you can use a resistive divider for Vgg2 in between Vdd and GND.
Q6: What is the recommended biasing sequence?
A6: Non self-biased amplifiers have a note below the electrical spec table saying,
The recommended power up biasing sequence is as follows.
Q7: Will Idd is going to change with Pin?
A7: The typical Idd value given on the DS is quiescent current, which can change with input power level. The change in Idd with Pin generally occurs with Power Amplifiers. You can refer to `Power Dissipation vs Input Power` and PAE curves given on the DS, to understand the behaviour of the amplifier better.