How can I manage power supply droop for ADTR1107 FE ICs in a TDD system with tight space constraints? I can't locate large capacitors beside each ADTR1107.

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You might find the ADAR1000EVAL1Z (STINGRAY) reference design useful. This design consists of 32 x ADTR1107 along with 8 x ADAR1000, and each ADTR1107 is given a 4.7uF capacitor. The system is powered from a single 5V supply, and power supply droop has not been reported as an issue. More information about the design, including a full schematic, can be found on the wiki site: https://wiki.analog.com/resources/eval/user-guides/stingray/userguide. Additionally, when using ADTR1107 in a large array, we recommend pulsing the gate rather than the drain. This means that 5V is always present at the VDD PA pin. The 4.7uF capacitor (adjacent to each ADTR1107's VDD pin in the Stingray design) acts as a local current reservoir which can re-charg during the Rx phase.

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How can I manage power supply droop for ADTR1107 FE ICs in a TDD system with tight space constraints? I can't locate large capacitors beside each ADTR1107.

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