What are the SPI parameters and communication structure for the ADF4368, and where can I find detailed documentation?

The ADF4368 uses SPI Mode 0 for communication. There is no command byte; only a 15-bit address, R/W bit, and 8-bit value need to be sent to the device. For detailed protocol properties, refer to AN-1248 available at https://www.analog.com/en/resources/app-notes/an-1248.html.

How can I ensure the ADF4368 is locked to a new frequency and measure the settling time during frequency sweeps?

You can use the lock detector in the ADF4368 to ensure the device is locked to a new frequency. Adjust the lock detect window (LDWIN) and lock detect count (LD_COUNT) values according to your application requirements. Reading the Lock Detect GPO or Register 0x0058, you can confirm that the ADF4368 is locked to the frequency. Pages 18-19 of the ADF4368 Datasheet provide an overview of the Lock Detector operation and recommended values for these settings. If the lock detect bit (Register 0x0058, bit 0) remains 0 despite the frequency appearing on a spectrum analyzer, ensure that the PD_LD bit (Register 0x2B [3]) is set to 0 and that Register 0x10 is written at the end of the SPI sequence. Additionally, check if the CSB pin is being driven to a defined state (logic 1, 1.8V) when the controller is removed, as an undefined state on the CSB pin can affect the LKDET pin behavior.

How can the noise random jump issue (walking spurs) be resolved when using the ADF4368 to output a series of 20MHz step frequencies with a 250MHz PFD in fractional mode?

These random spur jumps, known as walking spurs, can be reduced by lowering the loop bandwidth. The ADF4368 includes two mechanisms to address this issue: the bleed mechanism and the fractional engine modification. The bleed mechanism involves providing a small constant current at the charge pump, which can be fine-tuned using the BLEED_WORD bitfield. The PHASE_WORD value (registers 0x0023, 0x0022, 0x0021) can also be modified to eliminate fractional spurs. Changing the PHASE_WORD to 0xF00009 has been shown to help with the spurs. Note that the PHASE_WORD is double-buffered, so register 0x0010 should be written after updating the phase word.