I am attempting to control an ADF4382 PLL over SPI and I have noticed that when the PLL locks, the frequency is often slightly off from what I intended to program. What could be causing this?

The issue is related to the Integer Mode versus Fractional Mode setting. The INT_MODE bit in register 0x0015, bit 2, must be set based on the value of FRAC1WORD. If FRAC1WORD is 0, INT_MODE should be set to 1, indicating integer mode. If FRAC1WORD is non-zero, INT_MODE should be set to 0, indicating fractional mode. This ensures that the fractional part is used, allowing for accurate frequency generation that is not limited to integer multiples of the reference frequency.