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ADF41513 Recommended for New Designs
The ADF41513 is an ultralow noise frequency synthesizer that can be used to implement local oscillators (LOs) as high as 26.5 GHz in the upconversion and...
Datasheet
ADF41513 on Analog.com

Table of Contents

What is the required wait time between asserting Chip Enable (CE) and when the SPI inputs (CLK, DATA, LE) can be used on the ADF41513?

The required wait time between asserting Chip Enable (CE) and when the SPI inputs (CLK, DATA, LE) can be used on the ADF41513 depends on the value of the CReg1 decoupling capacitor. For a 1.1uF capacitor, the wait time is approximately 200us. For a 4.8uF capacitor (the datasheet recommendation), the wait time is approximately 450us. For a 20uF capacitor, the wait time is approximately 1.2ms.

Tags: Phase-Locked Loop (PLL) Synthesizers ADF41513 rf and microwave