Digital lock detect outputs high or low signal based on whether the PLL is locked or not. It decides this by measuring phase error for given set of time i.e. 15ns or 30ns.
Analog Lock Detect provides a open drain output signal and requires external circuitry to filter out the signal and to get the lock status. In MAX2880, you can setting register 30:27 to 0101 to get an ALD signal output from MUX pin which can be filtered out using RC circuit. Care should be taken care while designing this filter. Analog Lock Detect allows you to have more than just a 0 or 1 representation of a PLL lock status. The output voltage level can more accurately portray the lock status, so ALD can be used in any of application that requires more precision and accuracy than a digital one One downside to the ALD method is that it is slower than DLD .