What is the absolute maximum ratings for the excluded pins of the MAX2769C and MAX2769B?

Q. In the MAX2769B and MAX2769C datasheets, the Page 2 absolute maximum ratings do not include all the pins. What is the absolute maximum ratings for the excluded pins of the MAX2769C and MAX2769B? A. For the MAX2769C and MAX2769B the recommended value will be the same is indicated in the MAX2769 datasheet: Other Pins to GND ..................-0.3V to +(Operating VCC + 0.3V).

Is there a rad hard or space qualified version of the MAX2769?

Unfortunately, No. Maxim does not offer any rad hard or space qualified devices and does not conduct any radiation testing. There are no plans to do so in the foreseeable future.

What is the MAX2769 operating current?

The Supply Current specification listed in the datasheet Electrical Characteristics is for the 3V VCC supply only of the MAX2769, MAX2769B or MAX2769C device. When using the companion evaluation kit, be aware that the evaluation kit includes ±5 volt supplies that draw current which is not included in the MAX2769 datasheet specification.

Does the MAX2769 need a complete external oscillator circuit or does the device contain all of the components to use only an added crystal?

Both. Either an external reference oscillator or a crystal can be used with the MAX2769.

Can you read data from the three-wire interface (SPI) on the MAX2769?

The MAX2769 three-wire interface only has digital data input. We cannot read out the data in the internal registers.

How does the analog output impact the MAX2769 Noise Figure?

The noise figure of the MAX2769, when using the AGC gain setting is detailed according to the Cascaded Gain and Noise Figure vs. Temperature plot on sheet 5 of the datasheet. This characterization is done with an analog output mode when the ADC is bypassed. With this device, there are many possible configurations and not all of them have been characterized. The ADCs contribution to the NF would have little effect on the overall NF. When the MAX2769 LNA is cascaded with the PGA and other receiver blocks, the LNA's noise figure will dominate the overall noise figure according to the Friis equation, the ADC being at the tail-end of the system should have a marginal impact on the overall NF. TUTORIAL 1197 How Quantization and Thermal Noise Determine an ADC's Effective Noise Figure By: Daniel Terlep How Quantization and Thermal Noise Determine an ADC's Effective Noise Figure | Analog Devices TUTORIAL 5594 System Noise-Figure Analysis for Modern Radio Receivers By: Charles Razzell, Executive Director System Noise-Figure Analysis for Modern Radio Receivers | Analog Devices

Is it possible to drive two MAX2769 with one reference clock?

Q. Is it possible to drive two MAX2769 with one reference clock? A. It is possible to drive the MAX2769 with one reference clock. If the design is simply passing the X MHz refclk (XTAL pin) through without dividing or multiplying it to generate an ADC sampling clock of a higher/lower frequency, then the refclk is going through some logic gates then output as CLKOUT pin. Then it will be possible to drive two ICs with one reference clock.

Does the MAX2769 phase offset of the refclk vary between power cycles and temperature changes?

Q. Does the phase offset of the refclk vary widely between power cycles and temperature changes? Does Maxim characterize for the phase offset from IC to IC? A. The delay from XTAL to CLKOUT is not characterized. We expect it would be on the order of a couple of ns. It will vary somewhat with temperature. If both MAX2769s are co-located and presumably subject to the same temperature, this delay variation will tend to track. There may be slight part-to-part variation. The customer can observe the CLKOUT signals on an oscilloscope and confirm the above statements.

What is the required digital input logic-high for MAX2769 logic pins?

In the datasheet, under DC Electrical Characteristics, the Digital Input Logic-High MIN voltage is listed as 1.5V for SHDN\. Does this number apply to the other digital input pins ? Yes, the 1.5V value applies to all digital input pins. Similarly, the Digital Input Logic-Low 0.4V MAX applies to all digital input pins.

MAX2769 Power-up Register Initialization

There are ten registers in the MAX2769, including the last two that are "Reserved for test mode." It is required to program all ten registers upon power-up, and this includes the TEST1 and TEST2 registers which must be programmed to the default value shown in the Table 5. Default Register Settings. Failure to program all registers, including the TEST1 and TEST2 registers, can result in erroneous behavior. The electrical characteristics table includes a Note 1: MAX2769 is production tested at TA = +25°C. All min/max specifications are guaranteed by design and characterization from -40°C to +85°C, unless otherwise noted. Default register settings are not production tested or guaranteed. User must program the registers upon power-up.

Is the output clock (CLKOUT) phase-locked to the input clock (XTAL) on the MAX2769?

Q. Is the output clock (CLKOUT) phase-locked to the input clock (XTAL) on the MAX2769? A. The output clock CLKOUT is not “phase-locked” to the reference input clock XTAL.

When the IF filter of the MAX2769 is disabled, is it bypassed? i.e When bit 16 of configuration register 3 is set to 0, does it imply that the center frequency's bandwidth is larger than 18MHz?

To disable IF filters, low-pass filter would need to be selected. The bandwidth in this case is: +9MHz to -9MHz.

MAX2769 GAINREF with 1-bit Output

Q: The datasheet for the MAX2769 provides information on how to set the GAINREF value for 2-bit outputs, but how should it be set for a 1-bit output? A: Based on the way the AGC works, it shouldn't be used with a 1-bit output. The ADC quantizes the data into several levels, the number of levels dependent on the number of bits. For sign/magnitude encoding, the first bit is the sign (0 for positive, 1 for negative), and the rest of the bits are a magnitude. So for 4 bit operation, the quantization levels range from 1111 on the negative end to 0111 on the positive end. The GAINREF value tells the AGC what proportion of inputs will give an extreme code count (either 0111 or 1111). The AGC then scales the gain value to achieve this proportion. From this, it doesn't make sense to use AGC with a 1-bit output. The only outputs are 0 or 1, so every value is an "extreme value." Instead, gain should be adjusted manually to whatever provides the best SNR. The ADC will be acting as a comparator, looking at whether the input is above or below the midpoint, so a high gain value will likely provide the best results.

Does the MAX2769 retain the programmed setup during a power cycle?

No, the MAX2769 has no EEPROM memory to retain settings. All ten configuration registers must be programmed after a power cycle. See Note 1 under the Electrical Characteristics table in the MAX2769, MAX2769B and MAX2769C datasheets.

MAX2769C Power-up Register Initialization

There are ten registers in the MAX2769C, including the last two that are "Reserved for test mode." It is required to program all ten registers upon power-up, and this includes the TEST1 and TEST2 registers which must be programmed to the default value shown in the Table 22. Default Register Settings. Failure to program all registers, including the TEST1 and TEST2 registers, can result in erroneous behavior. The electrical characteristics table includes a Note 1: MAX2769C is production tested at TA = +25°C and +85°C. All min/max specifications are guaranteed by design and characterization from -40°C to +85°C, unless otherwise noted. Default register settings are not production tested or guaranteed. User must program the registers upon power-up.

What is the maximum sample rate for the MAX2769C's ADC?

What is the maximum sample rate for the MAX2769C's ADC? According to the MAX2769C's datasheet (page 16), it is stated that the ADC's maximum sampling rate is approximately 50Msps. While it is true that the ADC hardware can operate at 50Msps, the clock supplied to the ADC is limited to 32MHz for the MAX2769C. There are internal limitations that prevent the clock from exceeding 32 MHz. Therefore, the MAX2769C has a maximum sample rate of 32Msps. The MAX2771 uses the same ADC hardware and is capable of sampling at approximately 50Msps as long as the 50MHz clock is provided externally.