Question
We are trying to use HMC833LP6GE on the evaluation board. And we faced an
issue, which reveals as significant output clock distortion. We are using a
standard HMC833LP6GE evaluation board and the latest version of the supplied
software, including the recommended version of the register file. Using the
GUI, we configured different output frequencies and output
amplitudes. In the frequency range, where the VCO is divided (up to 1500MHz),
we did not see any problem. In the frequency range of 1500-3000 MHz (straight
readout of the VCO signal) significant duty cycle distortions were observed.
Reasonable jitter level (DDR mode measurements) was observed only when the
threshold level was far from the half of the amplitude. In case of frequency
doubler using (3000-6000MHz), the signal distortions were so high, that jitter
measurements were almost impossible. The level of the described signal
distortions depends on the chosen gain level.
Attached are oscilloscope snapshots for the following frequencies: 700MHz,
2000MHz, 3000MHz, 3050 MHz (eye diagram) and 3500MHz,
Answer
This is a normal behaviour. In doubler mode the waveform will not be a clean
sinewave since we simply connect P and N differential outputs together to
generate 2x the VCO frequency. The output signal contains the following
harmonics:
Note the ½ fo harmonic is very high (-4 dBc).
We don’t actually specify duty cycle for this part. If you require a 45-55%
duty cycle the output divider must be turned on with double off. This
restricts the available output frequencies to between 25MHz and 1500MHz. Even
with these large harmonics and non 50% duty cycle the jitter performance is
quite good. If you are using an Oscilloscope to measure jitter the scope
should be triggered off the 50MHz reference.
From DS: