Question
Based on the ADI recommended clock distribution network pdf please find the
following questions:
1) Working from the output levels in the HMC988 datasheet, I assume that
the HMCAD1511 will require OVDD = +3.3V to allow for the large LVPECL swing
into CLKP/N. Is this correct ?
2) The HMCAD1511 datasheet does not quote a current consumption number for OVDD
when running from +3V3, which will be required to size the voltage regulator.
Do you have a number that I can work with ?
3) For OVDD = +3.3V, I am assuming that the following will require/allow
signals at +3V3 signaling levels: CS, SDATA, SCLK, RESET and PD. Can you
confirm please.
4) What do I assume for the LVDS common mode outputs when OVDD = +3.3V ? Is it
affected at all ?
5) Is there a specific sequence during power-on, or restrictions that apply
when OVDD is different from the other power supplies to the HMCAD1511 ?
Specifically, does it matter if OVDD precedes AVDD and DVDD ?
Answer
1 The HMCAD1511 CLK inputs are AC-coupled internally so no additional
configuration changes are needed within the ADC to accept the default LVPECL
(800mVpp Single Ended, 1.6Vppd Differential) Clock signaling output directly
from the HMC988 while operating the HMCAD1511 from the nominal 1.8V OVDD
supply. The standard LVPECL termination scheme shown in your circuit proposal
is correct.
2. The HMCAD1511 OVDD supply domain powers only the Digital CMOS Logic and
Clock Inputs which are inherently low leakage CMOS inputs spec’d at +/-10uA
max. Even if the OVDD supply needed to be raised to 3.3V for certain legacy
CMOS compatibility I wouldn’t expect the current draw/demand from the OVDD
supply rail to increase very much, if at all, beyond the specified +/-10uA max
per CMOS input pin. As noted above, there’s really no inherent reason why the
customer should have to increase the HMCAD1511 OVDD supply above the nominal
1.8V level to interface with the LVPECL Clock coming from the HMC988, even if
the HMC988 itself is biased using a 3.3V supply.
3. Yes, the HMCAD1511 Digital CMOS Logic VIH/VIL input compatibility levels
track the OVDD supply. Unless the customer specifically needs 3.3V Input Logic
compatibility they can/should run OVDD at the nominal 1.8V level.
4. The OVDD supply domain biases only the Digital CMOS/CLK Inputs to
accommodate flexible interfacing to customer’s external 1.7V to 3.6V Control
Logic. The ADC’s Digital LVDS Output Drivers are biased from the nominal 1.8V
DVDD supply domain so they have no direct correlation to the Digital Input OVDD
supply domain.
5. The HMCAD1511 does offer an Aperture jitter control feature that allows a
user to set a trade-off between Power Consumption and Clock jitter. While this
feature doesn’t directly address any inherent min/max Aperture Delay
variability it will allow a user to “tighten up” the jitter on the CLK edge
from a nominal 160fsrms down to 120fsrms to at least minimize the variability
contribution due to CLK jitter as shown in Table 13 below.
We currently just have characterization value for the typical aperture values
as mentioned in DS.