Question Do you have the ThetaJC value for the ADF4106? in the datasheet I only find the thetJA Value. Answer ADF4106BRUZ use 16-lead TSSOP package (option RU-16). For this package we have the following number for theta JC: 27.6 (for standard 2-layer board, JEDEC 1S Standard); we do not have data for JEDEC 2S2P board type.

ADF4106: A and B counter calculation

Question I'm working on PLL synthesizer on frequency range up to 18GHz, I have gone through the data sheet of ADF4106 , now i'm interested in working upto 18 GHZ as so I found that in the frequency range from 13GHz to 18GHz the A and B counter values of N divider are not satisfying the condition that B must be greater than or equal to A. Answer The value of B must be greater or equal to A. Please refer to the attached application note on PLL for the N counter structure. For the possible N value, it should be in the range of Nmin =(Bmin × P)+ Amin =((P – 1) × P)+0 = P2– P Nmax= (Bmax × P)+ Amax Pls refer to the attached for the details. You can determine the B first to let the N is between BP and (B+1)P and select the proper A afterwards. I would recommend you use ADIsimPLL to simulate your design. The software will give you the proper B and A value. The ADIsimPLL software can be downloaded from ADI website.

ADF4106 PLL AVDD & DVDD working at a 5V

Question using +5V on AVDD and DVDD on ADF4106 and seem to work well. Is there any problem to use this voltage? We did not see any unsusual current draw and the operation seem to be very ok. The datasheet states a max +3.3V for DVDD but it seem to work very fine with +5V. As long as the device operate well and not rush any current, is there any internal voltage limitations? We had many devices running at +5V for many years already and did not see any problems. Is that ok to run at +5V? It seem to work very well at +5V. Please advice. Answer Thought it will work well at 5v, and reportly some customer have not seen any failure, spec issues or long term reliable issues of operation. As well as no issues were observed regarding EMC/EMI. Due to legal reasons, we can only go by what's in the datasheet. If customers are happy and works to their satisfaction. That's fine as long as they understand that we can not support it nor recommend this due to legal reason.

ADF4106: Is there any difference in phase noise performance when using different pre-scaler values for the same N value?

Question Is there any difference in phase noise performance when using different pre-scaler values for the same N value? - Not measured any difference Answer The phase noise is primarily affected by the value of N, Charge pump current, loop bandwidth and choice of VCO. We have not seen any difference in phase noise for difference values of P for the same value of N. At low output frequencies, the value of N can be realized in number of different ways (N=BP+A). At higher frequencies you may not have a choice in the value of the P as you are limited by the maximum clock speed of the CMOS A and B counters (about 300MHz). The ADF4106 uses an anti-backlash pulse to prevent dead zones in the PFD transfer function and improve phase noise performance. The function of the charge pump is to output current pulses proportional to the phase difference between the R counter and the N counter. Even when the difference is zero (or almost zero) the charge pump still outputs pulses, as the anti-backlash pulse is inserted to ensure that there is no dead-zone (this minimizes phase noise and spurs). The anti-backlash pulse width is 2.9ns default and 1.5ns minimum (set by ABP1 and ABP2 in the Reference Counter Latch). In general we recommend using the higher delays (2.9 & 6.0 ns), but if your PFD frequency is large, you may need to use the shorter delay. If you haven’t already done so, I recommend you Download ADI SimPLL from www.analog.com/adisimpll This simulation software for ADI synthesizer products will allow you to predict and optimize the phase noise performance in your specific application.

What is the charge pump value and how is it set in the ADF4106?

Question What is the charge pump value and how is it set in the ADF4106? Answer All our frequency synthesizers are current output devices and are quoted with a sensitivity of current per radian. Kd = 2.5mA is the charge pump current setting per 2pi radians (i.e. (2.5/2pi)mA per radian. The ADF4106 charge pump current setting is programmed by the current setting bits in the function latch map (Table 9 on page 15 of datasheet RevD). When the required frequency is changed the ADF4106 will produce a DC current for a very short period of time followed by current pulses which reduce in size as lock is approached. Once lock is detected, the current pulses are too minute to be measurable. The loop filter acts to integrate these current pulses into a voltage applied to the VCO. You can use ADIsimPLL to design the loop filter (https://form.analog.com/Form_Pages/RFComms/ADISimPll.aspx)

ADF4106: Kv changes phase margin

Question 1.How should I design the LPF of ADF4106 when producing a range of equal spaced output frequency? PD=250kHz，output frequency: 2000-4000MHz，using active loop filter configuration, OP184. I tried to use ADISIMPLL to simulate, it can give the result but I am not sure whether the Loop Filter's value need to be modified when the output frequency is changed? 2.How about the min PD and channel spacing of ADF4106 ？ 3.Can +24V power-supply voltage of OP184 make sure the output:OP184 VOH>=18V， VOL<=0.5V？ Answer 1. This depends on the VCO's Kv. if Kv is changed from one frequency to another, then you will see different loop bandwidth and phase margin result (with the same loop filter value). If VCO's Kv is vary a lot, it may cause the loop to become unstable at that frequency, you can change the ICP to compensate for the Kv changes. 2. Detector phase is nominally input frequency divided by R. 3. When the power supply is single 5V, the signal range is GND+0.125 to VDD-0.15V (as the figures),so it is OK for your requirement.

ADF4106_N counter output amplitude at MUXOUT-2

Question I use the 10MHz reference source with R-counter set as 1. The output from the VCO is at 2.38GHz. The prescalar is set as 8/9 using the AD evaluation software. I have measured without any component hanging on MUXOUT. The measured voltage level for N-counter is only about 1V at the 10MHz locked frequency, while for the R-counter, it is around 3V. The same amplitudes are also observed using ADF4107. I have also tried using the ADF4157. Same phenomenon is observed for the N-counter voltage also, around 1V at MUXOUT. There is no such phenomenon from the N-divider/2, R-divider nor R-divider/2 outputs. All the voltage measured are around 3V. Is there any possible reason for the low amplitude for N-counter? Answer I checked both ADF4106 and ADF4157 Muxout. The level of N-divider output was the same. There is a difference of duty cycle between N-divider output and R-divider output. For R-divider output (and N divide by 2) duty cycle is 50%, for N divider output it's much smaller - around 10%. That doesn't matter on our eval board without any components on Muxout. for this case,it was resolved by changing a high bandwidth oscilloscope to measure the N counter output.

RF & Microwave

Documents ADF4106: FAQ

ADF4106: FAQ

Q: ADF4106_N counter output amplitude at MUXOUT-2

Question I use the 10MHz reference source with R-counter set as 1. The output from the VCO is at 2.38GHz. The prescalar is set as 8/9 using the AD evaluation software. I have measured without any component hanging on MUXOUT. The measured voltage level for N-counter is only about 1V at the 10MHz locked frequency, while for the R-counter, it is around 3V. The same amplitudes are also observed using ADF4107. I have also tried using the ADF4157. Same phenomenon is observed for the N-counter voltage also, around 1V at MUXOUT. There is no such phenomenon from the N-divider/2, R-divider nor R-divider/2 outputs. All the voltage measured are around 3V. Is there any possible reason for the low amplitude for N-counter? Answer I checked both ADF4106 and ADF4157 Muxout. The level of N-divider output was the same. There is a difference of duty cycle between N-divider output and R-divider output. For R-divider output (and N divide by 2) duty cycle is 50%, for N divider output it's much smaller - around 10%. That doesn't matter on our eval board without any components on Muxout. for this case,it was resolved by changing a high bandwidth oscilloscope to measure the N counter output.