Using ADF4002 with RFin upto 500Mhz and driven at 0dBm

Question We are using a ADF4002BRU and have noticed that the device works with RFin driven at 0dBM and upto 500MHz, although it only specified for operation up to 400MHz. I noticed the Rev B data sheet “Figure 5. RF Input Sensitivity” extends to 500MHz typical. We are interested to know: 1. Is operation above the specified frequency a repeatable/guaranteed feature of the ADF4002? 2. What are the best operating conditions help ensure the RF input functions at this higher frequency? 3. Is there any test data to verify what we are seeing that it is repeatable/guaranteed? Answer If you use the device beyond 400MHz the N counter will simply stop working because the frequency will be too fast for the CMOS counter. Sorry if Figure 5 has caused some confusion and this demonstrates the result for perhaps 1-3 devices. Furthermore the ADF4002 has been characterised over temperature for an RFin of upto 400Mhz only and hence cannot be guaranteed to work beyond 400MHz.

ADF4002’s RF_IN Pins can be or how to properly terminate them

Question: Using the ADF4002 PLL, how best to terminate unused inputs such as ADF4002 RF_IN_A and RF_IN_B Answer: Do not leave unuse input inputs floating. For the Unused RFIN pins can be terminated with a capacitor to ground, such as 1nF or 100pF.

Question Do you have the thetaJC Value for the ADF4002? In the datasheet I only find the ThetaJA Value Answer Both ADF4002BRUZ use 16-lead TSSOP package (option RU-16). For this package we have the following number for theta JC: 27.6 (for standard 2-layer board, JEDEC 1S Standard); we do not have data for JEDEC 2S2P board type.

Active loop filter_amplifier Ibias generates large leakage spur

Question I use ADF4002 and AD797 in phase lock loop,but there is very bad phase detect frequency leakage,why? Answer The offset current and Bias current of AD797 will cause leakage spur, they need to use a narrow loop bandwidth to suppress the spur.

Question The idea is to generate a 20.736MHz signal from 10 Mhz, with a PN < -140 dbc @100 Khz, < -130 dbc @ 1 Khz. According to datasheet the min REF is 20 Mhz, but could be less depending on slewrate. Answer Refin = 10Mhz is not a problem, for REFIN < 20 MHz, ensure SR > 50 V/ìsec, biased at AVDD/2. The following applies equally for the ADF400X …ADF41XX REFIN Signal Characteristics:What drive level is acceptable for the REFIN input?The signal level for REFIN is specified in our datasheets to have a voltage greater than 0.4Vpp or 0.8Vpp, and less than VDD, biased at VDD/2. TheREFIN input circuitry OF THE ADF41XX is biased at Vdd/2.· When the REFIN source and ADF41XX share a supply voltage, the REFIN signal can be connected directly.· When the REFIN source and ADF41XX do not share a supply voltage, the REFIN signal should be AC-coupled; typically a 1 nF capacitor isrecommended.For, best performance, does REFIN of ADF41XX accept both signals of sine wave and square wave?REFIN can be a square wave, a pure sine wave or a clipped sine wave, but must meet the datasheet requirements in terms of REFIN Sensitivity, REFINFrequency/Slew rate and nominal threshold of VDD/2.The following circuit note uses high speed clock buffers to extend the low frequency of a high performance phase locked loop( PLL).http://www.analog.com/en/circuits-from-the-lab/CN0290/vc.htmlTo get the best performance in terms of phase noise/spurs from the ADF41XX a very clean reference source is required. With reference to the ADF41XXdatasheet, our phase noise, figure of merit and spurs are all carried out using a very clean reference source. While this may not be practical in areal world application, it shows the performance of our part without significant noise from a reference sourceI'm trying to determine the type of clock I can use for the REFIN of an ADF41XX. The data sheets states that it is a CMOS input with threshold ofVDD/2 and can be DC or AC coupled.The choice between providing a DC-coupled, CMOS compatible square wave or AC-coupled clock signal depends on the available REFIN. – for example, ifyour reference signal is a 10 MHz sine wave signal, and meets the minimum requirements for Sensitivity and Slew rate, then you can simply AC coupleto REFIN.However, if you have an option to apply a square wave reference signal with sharp edges, you might consider it – increasing the slew rate of thefalling edge of the reference signal can improve the phase noise of the part.