ADF4350_EVB version difference

Question I want to know the version difference between the ADF4350 EVBs. Answer The EVAL-ADF4350EB1Z is recommended for most customer evaluations. The EVAL-ADF4350EB2Z is recommended for customers who need access to the auxiliary and primary RF outputs. The EVAL-ADF4350AEB1Z is used to evaluate the ADF4350A part, (which is a special version of the part, not available to open market). The CFTL-CN0134-EVALZ is used to evaluate the ADF4350 PLL part used with a wideband modulator, and refers directly to the CFTL-0134.

ADF4350: Charge pump leakage current

Question Do you have any data on the charge pump leakage current of ADF4350? Answer Leakage spur is quite low in ADF4350 as it is fractional-N PLL. You could set the leakage in ADIsimPLL, but the result will be invisible because it is filtered by loop bandwidth. The typical value of leakage is about 1nA.

ADF4350_amplitude settling time-2

Question Could you please let us know for ADF4350, the "Average amplitude settling time for frequency jump of +/- 80 MHz, to the accuracy of +/-0.1dB "? Answer My understanding is if frequency is settled then the amplitude will be settled.

ADF4350: Where can I find the ADF4350 EVB Gerber Files?

Question Where can I find the ADF4350 EVB Gerber Files? Answer Please refer to the attached gerber files for ADF4350EB1Z

ADF4350: Worst case time for Power up to PLL phase lock?

Question I am using ADF4350 for 1030MHz and 1090MHz application. I programmed the PLL register for RF output stage disable with DB5 of Register 4. I wonder what is the time when setting the bit to enable its output. There will be output as soon as setting the bit to 1 or it needs to wait for the locking time – about 100us? And there is the same query about the time when power-down to power-up. Answer The worst case power up on the output stage is equal to the PLL lock time excluding VCO band select. So if the normal lock time from one channel to another is 130 us. Then the worst case lock time for output power-up from mute is 130 – 80 = 50 us. If output dividers are enabled, then the output stage powers up much faster, less than 10 us. But the worst case for this number is determined by the loop filter, which if the VCO is pulled, then the frequency jumps a little and has to settle. Power-up to PLL phase lock is determined by the loop bandwidth, plus the acquisition time of the loop filter. Using a 40 kHz filter, the lock time is around 130 us. 80 us from the band select process, 50 us from the PLL loop filter. Just to be clear. With the VCO powered up, and assuming a PLL loop bandwidth of 40 kHz, then the worst case lock time is about 50 us. With the VCO powered off, and keeping the same frequency, the lock time is similar, about 50 us. With the VCO powered off, and programming a new frequency (requiring band select), the lock time is about 80 us (band select) plus 50 us (PLL lock time) = 130 us.

ADF4350: Rset voltage at power up

Question Can we use the voltage of Rset pin to judge whether the ADF4350 works? I have used many type of our PLL products before. For those parts, Rset will be low voltage (about 0V) if the part doesn't work (power up but we don't config the part), and it will rise to nominal bias voltage(maybe 0.5V or so) when it works(after we config it). However, I find ADF4350's Rset voltage is 0.5V after power up even if we don't config it. It is different from other PLLs. Is it Normal? Answer The ADF4350 part will power up as soon as voltage is applied, this will lead to the Rset voltage powering up to it's bias level also. It differs in this manner from other PLL parts. You may use lock detect as a means of checking if the part works or not.

ADF4350: VCO and band selection delay and retaining register contents when CE is low

Question Q1: Does the VCO and band selection delay in the ADF4350 have to be allowed for when the VCO power down bit is toggled from off to on? Q2: Same as Q1 but for software power down bit and hardware CE line. Q3: Does the ADF4350 retain register contents when CE is low? Answer Q1 & Q2: Simply powering down the part (either hardware or software) means that the band information is retained. So if the part is being powered up at the SAME frequency then there is no delay. Q3: When in software power-down mode, the part retains all information in its registers. Only if the supply voltages are removed are the register contents lost.

ADF4350 EVB_Querying About Permittivity and Dielectric Materials

Question I am using Evaluation Board of ADF4350. And want to know the permittivity and the dielectric materials of the EVB. Answer We use Rogers 8 mils of 4003 dielectric material on the top and bottom of the board for the RF traces, and FR4 in the middle for traces that aren’t as critical. Rogers material has a permittivity constant 3.55. FR4 has a constant of 4.8.

ADF4350_output power variation over temperature

Question I want to know the output power variation of ADF4350 with temperature changing. Answer Power does vary with frequency and matching network.At a specific frequency with a specific matching network. The power variation is less than +/- 1 dB.

Phase Resync feature on the ADF4350

Question I am struggling to get the phase reseync feature enabled on my system. Do you have any reference guide or reference design that can help. Answer Please find attached the relevant documentation on this topic.

Question What difference among EVAL-ADF4350EB1Z, EVAL-ADF4350EB2Z, EVAL-ADF4350AEB1Z and CFTL-CN0134-EVALZ? Answer The EVAL-ADF4350EB1Z is recommended for most customer evaluations. The EVAL-ADF4350EB2Z is recommended for customers who need access to the auxiliary and primary RF outputs. The EVAL-ADF4350AEB1Z is used to evaluate the ADF4350A part, (which is a special version of the part, not available to open market). The CFTL-CN0134-EVALZ is used to evaluate the ADF4350 PLL part used with a wideband modulator, and refers directly to the CFTL-0134.

ADF4350 and ADF4108, charge pump settings for fast lock mode.

Question In ADF4108, there are two sets of charge pump setting to implement fast locking. But in ADF4350, just one set of charge pump settings, how does it work? Do they have the same working principle or just same as CSR (cycle slip reduction) ? Is it necessary to load R3 every time RF frequency changed? Can you explain in more detail? Answer The fast lock implementation in ADF4108 and ADF4350 are totally different. In ADF4108, the fast lock is achieved by changing the charge pump current, so the customer needs to program two charge pump settings, and program "CP GAIN" to switch between the two charge pump settings (fast lock mode1), or setting a timer to switch automatically after time out (fast lock mode 2) In ADF4350, fast lock is achieved by changing the 'SW' pin to GND or high impedance, so the customer needs to connect the SW pin to loop filter as in topology in the circuits in attached word document. This could be simulated by ADIsimPLL. and customer needs to set timer value to do the automatic switch, this is the same as ADF4108. ADF4350 also supports CSR (cycle slip reduction) which could improve locking time while loop bandwidth setting is too narrow (compare to PD frequency), it turns on(or off) a constant charge pump current and forces the tuning voltage to go in the right direction, and thus avoids cycle slip and improve locking time. CSR function will work automatically, so you only need to program R3 one time to enable this function. But there are two extra requirements to make CSR work correctly: 1. PD frequency needs to be 50% duty cycle. so if R counter is used, Ref div/2 also needs to be enabled to achieve 50% duty cycle; 2. ICP needs to set to a minimum value (0000) Some of the registers and bits are double buffered, that means after you write to these registers or bits, you have to write to R0 to make sure the part takes these values into action. For integer mode, the FRAC should be zero and you need to enable LDF bit to 1 to get integer lock detect.

Why do I see fractional spurs at multiples of 12.5Khz?

Question I am using an ADF4350 in fractional mode (see attached *.pll file),but first simulations gives poor results for phase noise at 12,5kHz from the carrier and for fractional spurious. Could you help me to improve phase noise in my design ? Answer In your settings the Modulus=768 and it is divisible by 2,3 or 6. Therfore, spurs will occur at one sixth of Fpdf/MOD, 19.2MHz/(768*6) = 4.1666Mhz, 8.333Khz, 12.5Khz etc. Therefore, reduce Modulus to say 25 and the spurs will ocurr at greater offsets from the carrier frequency, in this case 19.2Mhz/25 = 768Khz.

ADF4350_improve franctional spur

Question In my application,ADF4350 did not worked in expected RF frequency. I'm sure SPI communication is correct since R divided output can be viewed at MUXOUT. Initialization of ADF4350 setting: Fpfd = 16MHz,reference doble and div/2 used, 4GHz,MOD = 160 => A0h,INT = 250 => FAh,FRAC = 0 The registers setting as: R5 = 00 C0 00 05 R4 = 00 89 01 B4 R3 = 00 04 80 63 R2 = 13 00 60 C2 R1 = 08 00 85 01 R0 = 00 7D 00 00 Would you like to check and find any bug. Do the control software for the EVAL-ADF4350 can generate every register value? Answer You don't need to enable fast lock in register. And if the 16MHz reference input duty cycle is about 50%, that is ok for CSR, so they don't need to enable reference doublers and ref div/2 both. So I recommend you to change register value as below: R5 = 00580005 R4 = 00880034 R3 = 00040003 R2 = 000040C2 R1 = 08008501 R0 = 007D0000 our eval software can generate every register value, please see attached picture. BTW, if you need output step in 100kHz from 2.2G-4.4GHz, then you may find 50kHz/100kHz offset sub fractional spur or integer boundary spur very high in some frequency. in this case I suggest you to design a narrow loop bandwidth. for frequency range of 137.5MHz to 2.2GHz, you could use RF divider output. In this case VCO step could be x2 or x4, x8, x16 of 100kHz, fractional spur will be better attenuated.

Question I am using ADF4350 for frequency-sweeping. I want to know the delay time from one frequency to another. i.e. Ref freq = 10MHz PFD = 10MHz step size = 1MHz output freq range = 500MHz to 2 GHz what is the delay from one frequency to another? Answer This can be simulated with ADIsimPLL. But typically a frequency jump takes 100 – 200 us.

ADF4350_LD pin (pin25) and MUXOUT difference

Question There is a LD pin (pin 25) in ADF4350. What is the difference between this pin and the MUXOUT used as digital lock detect function? Answer LD is dedicate for Digital Lock Detect output, it is not related to register word, just a direct output of DLD signal; MUXOUT is more like a pin for debug or test purpose, it can output digital lock detect signal also, but need register program. it can also output ALD, VDD, R div, N div, etc. also need register programming.

What is the maximum current injection which the ADF4350's REFIN pin can accept?

Question What is the maximum current injection which the REFIN can accept? Answer The 60uA is what typically flows on that pin, but it rarely if ever reaches even 1mA. The voltage rating is the critical item here, if that is exceeded by 0.7V, then a protection diode will turn on, with the possibility of a large current flow occurring which could damage the circuitry, but the pin can handle quite a bit of current before long term damage results. For example, the latch-up tests are specified upto at least 100mA.

How should I terminate the RFoutA and RFoutB pins on the ADF4350?

Q. How should I terminate the RFoutA and RFoutB pins on the ADF4350? --------------------------------------------------------------------------------------------------- A. Well... 50 Ohm resistors directly to GND on the unused RFoutB pins are definitely not recommended! These unused RFout pins can be left floating, or AC coupled to GND with a 50 Ohm resistor, or connected with an RF choke to VDD and then AC coupled to GND with a 50 Ohm resistor. ADI has not seen any appreciable difference in performance between either setup. Regarding the used RF outputs RFoutA+/-: If a wide range of frequencies is covered, then 50 Ohm resistors to Vdd is preferable to the 390 nH/3.9 nH arrangement. The inductor network is good for a narrow range of frequencies, but parasitics/SRF etc can sometimes cause problems.

ADF4350 S-parameters by icollins Attached s-parameters for ADF4350 outputs. These were measured with RFoutA+/- output stage powered up at different power settings. RFoutA+ is connected to a network analyser while RFoutA- is connected to a 50 Ohm termination to GND. -Ian attachments.zip