Changing the ADF410X output channel without a glitch?

Question: During frequency sweeps, the PLL control voltage changes in a nice small signal manner, occasionally, something happens, and the control voltage goes to the positive rail for awhile, then settles at the correct Vtune. Can you explain the reason for this glitch and how to avoid it ? When changing channels using the ADF410X parts, in standard LO applications, a write to the N counter in sufficient to change the o/p frequency. This part has been used very successfully for many years in this type of application. More recently, the ADF410X family of parts has been designed in instrumentation applications, to generate a frequency sweep/ ramp generation, where very consistent short settling time on the V tune o/p is required. These customers have reported that occasionally during the ramp, the Vtune o/p shows a larger than normal glitch, resulting in longer settling time for certain frequency steps. This is a known issue on our older generation of PLL devices, which can be caused by either of the following scenarios. if the internal counters update before the digital logic associated with the SPI bus has settled to its correct value ( when changing channels ), incorrect data is loaded into the counters, but is re-loaded with correct data on next update of counters. Also explained as :” If the R counter has timed out to zero when the new contents are latched using LE then there is no R count for a brief period, and the PFD will think the feedback frequency is too high, and force CP down, (this looks to be happening). With VCXO’s this can be bad as if they rail it can take a long time for them to recover. …hence the glitch on V tune. The internal counters update on the falling edge of REFIN, so if you load new data from the SPI bus synchronized with the rising edge of REFIN, this will allow the digital logic a full half cycle of REFIN to settle before the next internal counter update. The recommended workaround for this issue, is to externally synchronize the rising edge of REFIN with the falling edge of LE, this will allow enough time for the digital logic to settle before the internal update of the counters takes place, and so avoid incorrect counter re-load. A simple flip-flop will do the job, ensuring that the LE pulse is gated by the rising edge of REFIN, meaning the timing delta between the two is always the same. In addition to ensure repeatable lock time a counter reset before the counters are loaded and released after they are loaded is required. This longer than expected settling time is very much application specific as it depends on the PFD used and the R divider value, and of course the settling time required following a channel change.

Explain how the ADF41XX datasheet PLL noise is specified?

The phase noise in an PLL can be described as having 2 components as shown in figure.1, a flat noise component known as the PLL Noise Floor, and a flicker 1/f Noise known as the PLL 1/f Noise. Figure.1 To reflect this in our datasheets, we have broken out our PLL phase noise specifications into two separate specifications, a Normalized phase noise floor (PN SYNTH ), and a Normalized 1/f Noise (PN 1_f ). PLL Noise Floor (PN TOT1 ) PN TOT1 = PN SYNTH + 20Log(N) + 10Log(F PFD ) (1) PN SYNTH (normalised noise floor in a 1Hz bandwidth) is very much device specific. N is the divider used by the PLL and F PFD is the frequency of the phase frequency detector. In order to accurately capture both PLL noise components, the loop bandwidth used to measure the PLL noise floor is 500kHz or greater. The VCO noise is high pass filtered inside the loop bandwidth, therefore using a wide instead of a narrow loop bandwidth will push more of the VCO noise out of band. PN TOT1 ( phase noise floor )is measured at an offset of 100kHz or greater. PN SYNTH ( Normalized phase noise floor) is then easily calculated by removing the 20Log(N) and the 10Log(F PFD ) contributions, see equation (1). For wide loop bandwidths, the normalized phase noise floor is the dominant PLL noise source. PLL 1/f Noise (PN TOT2 ) PN TOT2 = PN 1/f + 20Log(F RF /1GHz) + 10Log(10kHz/f) (2) F RF is the o/p RF frequency, and f = 1KHz(offset frequency where we measure PN TOT2 ). PN TOT2 (PLL 1/f noise) is measured at an offset of 1KHz. PN 1/f ( Normalized 1/f noise) is then calculated by removing t he 20Log(F RF /1GHz) and the 10Log(10kHz/f) contributions, see equation (2). Active devices, including the PLL charge pump, produce a flicker (1/f) noise. Equation (2) indicates that the PLL 1/f noise increases 20dBs per decade as a function of F RF and 10 dBs per decade as a function of f (offset frequency from the carrier). For narrow loop bandwidths, the normalized 1/f noise number is significant. These noise sources add together, giving a total PLL phase noise. Since noise sources add in root sum fashion, the larger noise source will dominate. ADIsimPLL Version3.3 and greater models both the noise floor and 1/f noise so you can accurately simulate PLL phase noise for the PLL loop design.

Digital Lock Detect output from the ADF4106 is not indicating lock correctly, why?

The ADF41XX family of integer –N PLL synthesizers offer two forms of lock detect: Analog Lock Detect ( ALD) and Digital Lock Detect ( DLD). The AN-873 application note explains both options to allow the user to make an informed decision as to which form of lock detect to use. The Phase Frequency Detector (PFD) produces outputs UP and DN in response to the frequency and phase difference at the inputs, namely the R counter and N counter outputs. The logical NOR of UP and DN is used as the source signal for both the ALD and DLD circuits. Figure 1. PFD and Charge Pump on the ADF4xxx Family of PLL Synthesizers The logical NOR of the PFD outputs in a locked state produces a logic high with low pulses, whose duration is set by the anti-backlash pulse width plus any additional leakage currents. Figure 2. Timing Diagram of PLL in Lock Showing the Reference Signal, Divided RF Signal, Q1 and Q2 (the Up and Down Pulses Going from the PFD to the Charge Pump), and the ALD Signal, which is the NOR of Q1 and Q2 Leakage currents can have a number of sources, most prominent are, VCXO’s, the charge pump, loop filter capacitors, and biasing currents for active loop filters. After filtering, ALD can have more than just a 0 or 1 representation of a PLL lock status. The output voltage level can more accurately portray the lock status, however, the filter must be designed carefully, and the rise and fall times of the output voltage level can be an issue in some applications. ADIsimPLL can be used to design the ALD external filter components. Digital lock detect is a CMOS logic output, whose status is logic high for a PLL lock. By its digital nature, DLD has to make a definite yes-or-no decision as to whether or not a PLL is in lock. Under certain circumstances, as described in application note AN-873, DLD is susceptible to inaccuracies. Through careful consideration of the PFD frequency and leakage currents flowing, it is possible to determine if DLD is accurate in a particular application. The Digital lock Detect circuit uses the logical NOR of the PFD outputs as its CLKIN source. Figure 3. Simplified Circuit Diagram for Digital Lock Detect; CLK IN is the Analog Lock Detect Signal As mentioned, this signal will have low going pulses, whose width will change depending on the anti-backlash pulse and leakage currents. In fact, the leakage currents act to increase the pulse width from its nominal value (which is the anti-backlash pulse width). The Digital lock detect circuit uses a set window of 15nsec pulse width to determine the lock status of the PLL. When CLKIN of the DLD circuit has a pulse width of less than 15nsec for 5 consecutive cycles, the DLD circuit indicates that the PLL is locked. Once the DLD circuit indicates lock, it now looks for a loss of lock. The loss of lock is detected when the pulse width of the CLKIN to the DLD circuit is equal to or greater than 30nsec on any subsequent PFD cycle. In applications where the leakage currents are large enough to increase the pulse width duration of CLKIN to greater than 15nsec, then DLD will not be able to indicate lock, even if the PLL is locked. In this case, the use of ALD is necessary. The set window for digital lock detect and loss of lock does not change over the usable PFD frequency change. Therefore it’s obvious that the accuracy of the digital lock detect is a function of the PFD frequency. The higher PFD frequency, the shorter will be the periods of the R counter and N counter signal to the PFD. Taking an example of a PFD frequency = 30MHz, the R and N counter periods will be equal to approximately 33nsec. In this case the accuracy of the digital lock is compromised as the unlocked frequency close to the desired frequency will cause the CLKIN feeding the DLD circuit to drift in and out of the 15nsec window. In this scenario the DLD signal will pulse high and low. In a more extreme case, using a PFD=100MHz, will result in signals at the PFD with a period of 10nsec. A frequency error in this application of 10 % would put the two PFD inputs within 1nsec of each other and the DLD will inaccurately indicate lock detect. In this application it is necessary to use ALD instead of DLD to indicate lock.

Q: What happens to the PLL when the REFIN is removed ?.

All our Frequency Synthesizers parts can have the Reference (REFIN) signal removed, and unlock will result. Reconnecting REFIN will result in the part locking to the correct frequency. ADF41xx parts will behave in this manner. Our Frequency Synthesizers (both Integer and Fractional) can be programmed without REFIN, and will lock to the correct frequency on application of the reference. For our Frequency Synthesizers with Integrated VCO’s, the REFIN can be removed leading to unlock, and on reapplication of REFIN the part will regain lock, h owever, REFIN must be present when locking the integrated parts after power-up or when changing to a new frequency. This is due to the presence of a multi-band VCO calibration circuit which uses feedback from the VCO frequency and the Reference frequency to choose the correct band. Without the REFIN signal, this calibration is not possible. The part will remain in the same band if REFIN is removed, so REFIN must be present on the integrated parts during frequency updates or errors will result. Our lock detect circuit provides an Analog Lock Detect ( ALD) signal and a Digital Lock Detect ( DLD) signal. For more details on this function , refer to AN-873. The DLD signal requires the presence of the REFIN signal in order to generate a reliable DLD signal, in applications where a reliable DLD signal is required in the absence of the REFIN signal, we recommend that the ALD signal is used instead of the DLD.

Q Do you have information on the phase noise of the dividers used in your current frequency synthesiser devices ? You publish total device phase noise performance, which is usually adequate, but I want to use the ADF4107 as a programmable divider, and I'm not able to model the system properly... A We have not evaluated the counters and charge pump separately. However, we do know that the CP is not a significant contributor to phase noise. We have deduced this by virtue of the fact that changing the CP current from 5mA to 625µA makes no difference to the overall phase noise. In theory, the best phase noise is achieved with max CP current. Therefore, it is safe to assume that the PN achieved when used as a counter will be much the same as the phase noise quoted in the data sheet.